// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_rp_cfgspace_2_c_union_define.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:02:58 Create file
// ******************************************************************************

#ifndef __HIPCIEC_RP_CFGSPACE_2_C_UNION_DEFINE_H__
#define __HIPCIEC_RP_CFGSPACE_2_C_UNION_DEFINE_H__

/* Define the union U_PCIHDR_ID */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    device_id : 16  ; /* [31:16] */
        unsigned int    vendor_id : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIHDR_ID;

/* Define the union U_PCIHDR_CMDSTS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_detected_par_err     : 1  ; /* [31] */
        unsigned int    cfg_rx_sys_err           : 1  ; /* [30] */
        unsigned int    cfg_rx_master_abort      : 1  ; /* [29] */
        unsigned int    cfg_rx_target_abort      : 1  ; /* [28] */
        unsigned int    cfg_sig_target_abort     : 1  ; /* [27] */
        unsigned int    cfg_devsel_timing        : 2  ; /* [26:25] */
        unsigned int    cfg_mdata_par_err        : 1  ; /* [24] */
        unsigned int    cfg_fastb2b_cap          : 1  ; /* [23] */
        unsigned int    rsv_0                    : 1  ; /* [22] */
        unsigned int    cfg_66mhz_cap            : 1  ; /* [21] */
        unsigned int    cfg_cap_list             : 1  ; /* [20] */
        unsigned int    cfg_intx_status          : 1  ; /* [19] */
        unsigned int    rsv_1                    : 2  ; /* [18:17] */
        unsigned int    immediate_readiness      : 1  ; /* [16] */
        unsigned int    rsv_2                    : 5  ; /* [15:11] */
        unsigned int    cfg_intx_disable         : 1  ; /* [10] */
        unsigned int    cfg_fast_b2b_en          : 1  ; /* [9] */
        unsigned int    cfg_serr_en              : 1  ; /* [8] */
        unsigned int    idsel_stepp_wait_cly_ctr : 1  ; /* [7] */
        unsigned int    cfg_parity_err_resp      : 1  ; /* [6] */
        unsigned int    cfg_vga_snoop_en         : 1  ; /* [5] */
        unsigned int    cfg_mem_wr_invld_en      : 1  ; /* [4] */
        unsigned int    cfg_special_cycle_en     : 1  ; /* [3] */
        unsigned int    cfg_master_en            : 1  ; /* [2] */
        unsigned int    cfg_mem_space_en         : 1  ; /* [1] */
        unsigned int    cfg_io_space_en          : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIHDR_CMDSTS;

/* Define the union U_PCIHDR_CLSREV */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    base_class_code : 8  ; /* [31:24] */
        unsigned int    sub_class_code  : 8  ; /* [23:16] */
        unsigned int    program_inf     : 8  ; /* [15:8] */
        unsigned int    revision_id     : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIHDR_CLSREV;

/* Define the union U_PCIHDR_MISC */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    bist_cap          : 1  ; /* [31] */
        unsigned int    start_bist        : 1  ; /* [30] */
        unsigned int    rsv_3             : 2  ; /* [29:28] */
        unsigned int    bist_result       : 4  ; /* [27:24] */
        unsigned int    multi_func_deivce : 1  ; /* [23] */
        unsigned int    cfg_header_type   : 7  ; /* [22:16] */
        unsigned int    cfg_latency_timer : 8  ; /* [15:8] */
        unsigned int    cfg_cachlie_size  : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIHDR_MISC;

/* Define the union U_PCIHDR_BAR0 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_bar0_addr        : 28  ; /* [31:4] */
        unsigned int    cfg_bar0_prefetch_en : 1  ; /* [3] */
        unsigned int    cfg_bar0_width       : 1  ; /* [2] */
        unsigned int    rsv_4                : 1  ; /* [1] */
        unsigned int    cfg_bar0_type        : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIHDR_BAR0;

/* Define the union U_PCIHDR_BAR1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_bar1_addr        : 28  ; /* [31:4] */
        unsigned int    cfg_bar1_prefetch_en : 1  ; /* [3] */
        unsigned int    cfg_bar1_width       : 2  ; /* [2:1] */
        unsigned int    cfg_bar1_type        : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIHDR_BAR1;

/* Define the union U_PCIHDR_BUS_NUM */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sec_lat_timer : 8  ; /* [31:24] */
        unsigned int    sub_bus_num   : 8  ; /* [23:16] */
        unsigned int    sec_bus_num   : 8  ; /* [15:8] */
        unsigned int    pri_bus_num   : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIHDR_BUS_NUM;

/* Define the union U_PCIHDR_IO_LIMIT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sec_detect_parity_err      : 1  ; /* [31] */
        unsigned int    sec_received_system_err    : 1  ; /* [30] */
        unsigned int    sec_received_master_abort  : 1  ; /* [29] */
        unsigned int    sec_received_target_abort  : 1  ; /* [28] */
        unsigned int    sec_signal_target_abort    : 1  ; /* [27] */
        unsigned int    sec_devsel_timing          : 2  ; /* [26:25] */
        unsigned int    sec_master_date_parity_err : 1  ; /* [24] */
        unsigned int    sec_fast_b2b_cap           : 1  ; /* [23] */
        unsigned int    rsv_5                      : 1  ; /* [22] */
        unsigned int    sec_66mhz_cap              : 1  ; /* [21] */
        unsigned int    rsv_6                      : 5  ; /* [20:16] */
        unsigned int    cfg_io_low_limit           : 4  ; /* [15:12] */
        unsigned int    cfg_io_low_limit_sup       : 4  ; /* [11:8] */
        unsigned int    cfg_io_low_base            : 4  ; /* [7:4] */
        unsigned int    cfg_io_low_base_sup        : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIHDR_IO_LIMIT;

/* Define the union U_PCIHDR_MEM_BASE_LIMIT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    mem_limit : 12  ; /* [31:20] */
        unsigned int    rsv_7     : 4  ; /* [19:16] */
        unsigned int    mem_base  : 12  ; /* [15:4] */
        unsigned int    rsv_8     : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIHDR_MEM_BASE_LIMIT;

/* Define the union U_PCIHDR_PRE_MEM_BASE_LIMIT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    prefetch_mem_limit_h : 12  ; /* [31:20] */
        unsigned int    prefetch_mem_limit_l : 4  ; /* [19:16] */
        unsigned int    prefetch_mem_base_h  : 12  ; /* [15:4] */
        unsigned int    prefetch_mem_base_l  : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIHDR_PRE_MEM_BASE_LIMIT;

/* Define the union U_PCIHDR_PRE_MEM_BASE_32_UPADR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    prefetch_mem_base_up32bit : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIHDR_PRE_MEM_BASE_32_UPADR;

/* Define the union U_PCIHDR_PRE_MEM_LIMIT_32_UPADR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    prefetch_mem_limit_up32bit : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIHDR_PRE_MEM_LIMIT_32_UPADR;

/* Define the union U_PCIHDR_IO_UPADR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    io_limit_up16bit : 16  ; /* [31:16] */
        unsigned int    io_base_up16bit  : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIHDR_IO_UPADR;

/* Define the union U_PCIHDR_CAPPTR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_9       : 24  ; /* [31:8] */
        unsigned int    cfg_cap_ptr : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIHDR_CAPPTR;

/* Define the union U_PCIHDR_EXP_ROM_BASE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    ext_rom_base_address : 21  ; /* [31:11] */
        unsigned int    rsv_10               : 10  ; /* [10:1] */
        unsigned int    ext_rom_enable       : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIHDR_EXP_ROM_BASE;

/* Define the union U_PCIHDR_INT */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_11                      : 4  ; /* [31:28] */
        unsigned int    bridge_timer_serr_en        : 1  ; /* [27] */
        unsigned int    bridge_discard_timer_status : 1  ; /* [26] */
        unsigned int    bridge_sec_discard_timer    : 1  ; /* [25] */
        unsigned int    bridge_pri_discard_timer    : 1  ; /* [24] */
        unsigned int    bridge_fast_b2b_en          : 1  ; /* [23] */
        unsigned int    bridge_sec_bus_reset        : 1  ; /* [22] */
        unsigned int    bridge_master_abort_mode    : 1  ; /* [21] */
        unsigned int    bridge_vga16bit_decode      : 1  ; /* [20] */
        unsigned int    bridge_vga_en               : 1  ; /* [19] */
        unsigned int    bridge_isa_en               : 1  ; /* [18] */
        unsigned int    bridge_serr_en              : 1  ; /* [17] */
        unsigned int    bridge_parity_err_resp_en   : 1  ; /* [16] */
        unsigned int    cfg_int_pin                 : 8  ; /* [15:8] */
        unsigned int    cfg_int_line                : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIHDR_INT;

/* Define the union U_PCIE_CAP_HEADER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_12             : 1  ; /* [31] */
        unsigned int    undefine_00        : 1  ; /* [30] */
        unsigned int    int_msg_num        : 5  ; /* [29:25] */
        unsigned int    slot_implement     : 1  ; /* [24] */
        unsigned int    port_type          : 4  ; /* [23:20] */
        unsigned int    pci_cap_ver        : 4  ; /* [19:16] */
        unsigned int    pcie_next_cap_addr : 8  ; /* [15:8] */
        unsigned int    pci_capid          : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PCIE_CAP_HEADER;

/* Define the union U_DEVICE_CAPBILITY */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_13                   : 3  ; /* [31:29] */
        unsigned int    flr_cap                  : 1  ; /* [28] */
        unsigned int    cap_slot_pwr_sca         : 2  ; /* [27:26] */
        unsigned int    cap_slot_pwr_limit_val   : 8  ; /* [25:18] */
        unsigned int    rsv_14                   : 2  ; /* [17:16] */
        unsigned int    ro_base_err_rpt          : 1  ; /* [15] */
        unsigned int    undefine_04              : 3  ; /* [14:12] */
        unsigned int    ep_l1_accept_lat         : 3  ; /* [11:9] */
        unsigned int    ep_l0s_accept_lat        : 3  ; /* [8:6] */
        unsigned int    ext_tag_sup              : 1  ; /* [5] */
        unsigned int    phantom_fun_sup          : 2  ; /* [4:3] */
        unsigned int    max_payload_size_support : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DEVICE_CAPBILITY;

/* Define the union U_DEVICE_CTRL_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_15                   : 9  ; /* [31:23] */
        unsigned int    emergency_pwr_reduce_det : 1  ; /* [22] */
        unsigned int    tlp_pending              : 1  ; /* [21] */
        unsigned int    aux_pwr_detect           : 1  ; /* [20] */
        unsigned int    ur_detect                : 1  ; /* [19] */
        unsigned int    fat_err_detect           : 1  ; /* [18] */
        unsigned int    non_fata_detect          : 1  ; /* [17] */
        unsigned int    cor_err_detect           : 1  ; /* [16] */
        unsigned int    rsv_16                   : 1  ; /* [15] */
        unsigned int    max_read_req_size        : 3  ; /* [14:12] */
        unsigned int    no_snoop_en              : 1  ; /* [11] */
        unsigned int    aux_pwr_pm_en            : 1  ; /* [10] */
        unsigned int    phantom_func_en          : 1  ; /* [9] */
        unsigned int    extend_tag_en            : 1  ; /* [8] */
        unsigned int    max_payload_size         : 3  ; /* [7:5] */
        unsigned int    relax_order_en           : 1  ; /* [4] */
        unsigned int    ur_rpt_en                : 1  ; /* [3] */
        unsigned int    fat_err_rpt_en           : 1  ; /* [2] */
        unsigned int    non_fat_rpt_en           : 1  ; /* [1] */
        unsigned int    cor_err_rpt_en           : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DEVICE_CTRL_STATUS;

/* Define the union U_LINK_CAPBILITY */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    port_num                : 8  ; /* [31:24] */
        unsigned int    rsv_17                  : 1  ; /* [23] */
        unsigned int    aspm_opt_compliance     : 1  ; /* [22] */
        unsigned int    link_band_notice_cap    : 1  ; /* [21] */
        unsigned int    dl_link_act_rpt_cap     : 1  ; /* [20] */
        unsigned int    surprise_dn_err_rpt_cap : 1  ; /* [19] */
        unsigned int    clock_pm                : 1  ; /* [18] */
        unsigned int    l1_exit_lat             : 3  ; /* [17:15] */
        unsigned int    l0_exit_lat             : 3  ; /* [14:12] */
        unsigned int    aspm_sup                : 2  ; /* [11:10] */
        unsigned int    max_link_width          : 6  ; /* [9:4] */
        unsigned int    max_link_speed          : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_LINK_CAPBILITY;

/* Define the union U_LINK_CTRL_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    link_auto_band_status : 1  ; /* [31] */
        unsigned int    link_band_status      : 1  ; /* [30] */
        unsigned int    dl_cfg_link_active    : 1  ; /* [29] */
        unsigned int    slot_clk_cfg          : 1  ; /* [28] */
        unsigned int    link_training         : 1  ; /* [27] */
        unsigned int    undefined_12          : 1  ; /* [26] */
        unsigned int    mac_cur_link_width    : 6  ; /* [25:20] */
        unsigned int    mac_cur_link_speed    : 4  ; /* [19:16] */
        unsigned int    drs_signal_ctrl       : 2  ; /* [15:14] */
        unsigned int    rsv_18                : 2  ; /* [13:12] */
        unsigned int    link_auto_band_int_en : 1  ; /* [11] */
        unsigned int    link_band_int_en      : 1  ; /* [10] */
        unsigned int    hw_auto_width_dis     : 1  ; /* [9] */
        unsigned int    clock_pm_en           : 1  ; /* [8] */
        unsigned int    extended_sync         : 1  ; /* [7] */
        unsigned int    common_clk_cfg        : 1  ; /* [6] */
        unsigned int    retrain_link          : 1  ; /* [5] */
        unsigned int    link_disable          : 1  ; /* [4] */
        unsigned int    rcb                   : 1  ; /* [3] */
        unsigned int    rsv_19                : 1  ; /* [2] */
        unsigned int    aspm_ctrl             : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_LINK_CTRL_STATUS;

/* Define the union U_SLOT_CAPABILITY */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    physical_slot_num    : 13  ; /* [31:19] */
        unsigned int    no_comman_cpled_sup  : 1  ; /* [18] */
        unsigned int    elec_interlock_pre   : 1  ; /* [17] */
        unsigned int    slot_pwr_limit_scale : 2  ; /* [16:15] */
        unsigned int    slot_pwr_limit_val   : 8  ; /* [14:7] */
        unsigned int    hot_plug_cap         : 1  ; /* [6] */
        unsigned int    hot_plug_surprise    : 1  ; /* [5] */
        unsigned int    pwr_indicator_pre    : 1  ; /* [4] */
        unsigned int    att_indecator_pre    : 1  ; /* [3] */
        unsigned int    msl_sensor_pre       : 1  ; /* [2] */
        unsigned int    pwr_ctrl_pre         : 1  ; /* [1] */
        unsigned int    att_button_pre       : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SLOT_CAPABILITY;

/* Define the union U_SLOT_CTRL_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_20                 : 7  ; /* [31:25] */
        unsigned int    dl_state_change        : 1  ; /* [24] */
        unsigned int    elec_interlock_st      : 1  ; /* [23] */
        unsigned int    presencd_det_st        : 1  ; /* [22] */
        unsigned int    mrl_sensor_st          : 1  ; /* [21] */
        unsigned int    command_cpled          : 1  ; /* [20] */
        unsigned int    presencd_det_change    : 1  ; /* [19] */
        unsigned int    mrl_sensor_change      : 1  ; /* [18] */
        unsigned int    pwr_fault_det          : 1  ; /* [17] */
        unsigned int    attention_button       : 1  ; /* [16] */
        unsigned int    rsv_21                 : 2  ; /* [15:14] */
        unsigned int    auto_slot_plmt_disable : 1  ; /* [13] */
        unsigned int    dl_state_change_en     : 1  ; /* [12] */
        unsigned int    elec_interlock_ctrl    : 1  ; /* [11] */
        unsigned int    pwr_ctrled_ctrl        : 1  ; /* [10] */
        unsigned int    pwr_indicator_ctrl     : 2  ; /* [9:8] */
        unsigned int    att_indicator_ctrl     : 2  ; /* [7:6] */
        unsigned int    hot_plug_int_en        : 1  ; /* [5] */
        unsigned int    command_cpled_int_en   : 1  ; /* [4] */
        unsigned int    presence_det_change_en : 1  ; /* [3] */
        unsigned int    mrl_sensor_change_en   : 1  ; /* [2] */
        unsigned int    pwr_fault_det_en       : 1  ; /* [1] */
        unsigned int    att_buttom_pre_en      : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SLOT_CTRL_STATUS;

/* Define the union U_ROOT_CTRL_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_22                : 15  ; /* [31:17] */
        unsigned int    crs_sw_visibility     : 1  ; /* [16] */
        unsigned int    rsv_23                : 11  ; /* [15:5] */
        unsigned int    crs_sw_visibility_en  : 1  ; /* [4] */
        unsigned int    pme_int_en            : 1  ; /* [3] */
        unsigned int    sys_err_on_fat_err_en : 1  ; /* [2] */
        unsigned int    sys_err_on_non_fat_en : 1  ; /* [1] */
        unsigned int    sys_err_on_cor_err_en : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_ROOT_CTRL_STATUS;

/* Define the union U_ROOT_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_24        : 14  ; /* [31:18] */
        unsigned int    pme_pending   : 1  ; /* [17] */
        unsigned int    pme_status_rt : 1  ; /* [16] */
        unsigned int    pme_rid       : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_ROOT_STATUS;

/* Define the union U_DEVICE_CAPABILITY2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    frs_sup                       : 1  ; /* [31] */
        unsigned int    rsv_25                        : 4  ; /* [30:27] */
        unsigned int    emergency_pwr_reduce_init_req : 1  ; /* [26] */
        unsigned int    emergency_pwr_reduce_sup      : 2  ; /* [25:24] */
        unsigned int    max_end_end_pfx               : 2  ; /* [23:22] */
        unsigned int    end_end_pfx_sup               : 1  ; /* [21] */
        unsigned int    ext_fmt_sup                   : 1  ; /* [20] */
        unsigned int    obff_sup                      : 2  ; /* [19:18] */
        unsigned int    sup_10bit_req_tag             : 1  ; /* [17] */
        unsigned int    sup_10bit_cpl_tag             : 1  ; /* [16] */
        unsigned int    ln_sys_cls                    : 2  ; /* [15:14] */
        unsigned int    tph_cpl_sup                   : 2  ; /* [13:12] */
        unsigned int    ltr_mech_sup                  : 1  ; /* [11] */
        unsigned int    no_roen_prpr_pass             : 1  ; /* [10] */
        unsigned int    cas_128bit_cpl_sup            : 1  ; /* [9] */
        unsigned int    atomic_64bit_cpl_sup          : 1  ; /* [8] */
        unsigned int    atomic_32bit_cpl_sup          : 1  ; /* [7] */
        unsigned int    atomicop_route_sup            : 1  ; /* [6] */
        unsigned int    ari_fwd_sup                   : 1  ; /* [5] */
        unsigned int    cpl_timeout_disable_sup       : 1  ; /* [4] */
        unsigned int    cpl_timeout_range             : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DEVICE_CAPABILITY2;

/* Define the union U_DEVICE_CTRL2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_26                   : 16  ; /* [31:16] */
        unsigned int    end_end_pfx_blk          : 1  ; /* [15] */
        unsigned int    obff_en                  : 2  ; /* [14:13] */
        unsigned int    en_10bit_req_tag         : 1  ; /* [12] */
        unsigned int    emergency_pwr_reduce_req : 1  ; /* [11] */
        unsigned int    ltr_mech_en              : 1  ; /* [10] */
        unsigned int    ido_cpl_en               : 1  ; /* [9] */
        unsigned int    ido_req_en               : 1  ; /* [8] */
        unsigned int    atomicop_egress_blk      : 1  ; /* [7] */
        unsigned int    atomicop_req_en          : 1  ; /* [6] */
        unsigned int    ari_fwd_en               : 1  ; /* [5] */
        unsigned int    cpl_timeout_dis          : 1  ; /* [4] */
        unsigned int    cpl_timeout_value        : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DEVICE_CTRL2;

/* Define the union U_LINK_CAPABILITY2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    drs_sup                      : 1  ; /* [31] */
        unsigned int    rsv_27                       : 6  ; /* [30:25] */
        unsigned int    retimer2_presence_detect_sup : 1  ; /* [24] */
        unsigned int    retimer_presence_detect_sup  : 1  ; /* [23] */
        unsigned int    cfg_rx_lower_skp_cap         : 7  ; /* [22:16] */
        unsigned int    cfg_tx_lower_skp_cap         : 7  ; /* [15:9] */
        unsigned int    cross_link_sup               : 1  ; /* [8] */
        unsigned int    link_speed_sup               : 7  ; /* [7:1] */
        unsigned int    rsv_28                       : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_LINK_CAPABILITY2;

/* Define the union U_LINK_CTRL_STATUS2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    drs_msg_recved                : 1  ; /* [31] */
        unsigned int    downstream_component_presence : 3  ; /* [30:28] */
        unsigned int    rsv_29                        : 2  ; /* [27:26] */
        unsigned int    crosslink_resolution          : 2  ; /* [25:24] */
        unsigned int    retimer2_presence_detect      : 1  ; /* [23] */
        unsigned int    retimer_presence_detect       : 1  ; /* [22] */
        unsigned int    link_8g_eq_req                : 1  ; /* [21] */
        unsigned int    eq_8g_phase3_success          : 1  ; /* [20] */
        unsigned int    eq_8g_phase2_success          : 1  ; /* [19] */
        unsigned int    eq_8g_phase1_success          : 1  ; /* [18] */
        unsigned int    eq_8g_complete                : 1  ; /* [17] */
        unsigned int    cur_deemp_level               : 1  ; /* [16] */
        unsigned int    compliance_preset_deemp       : 4  ; /* [15:12] */
        unsigned int    compliance_sos                : 1  ; /* [11] */
        unsigned int    enter_mod_compliance          : 1  ; /* [10] */
        unsigned int    transmit_margin               : 3  ; /* [9:7] */
        unsigned int    selectable_de_emphasis        : 1  ; /* [6] */
        unsigned int    hw_auto_speed_dis             : 1  ; /* [5] */
        unsigned int    enter_compliance              : 1  ; /* [4] */
        unsigned int    target_link_speed             : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_LINK_CTRL_STATUS2;

/* Define the union U_SLOT_CAP_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    slot_cap_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SLOT_CAP_2;

/* Define the union U_SLOT_CTRL_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    slot_ctrl_2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SLOT_CTRL_2;

/* Define the union U_MSI_CAP_HEADER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_30              : 7  ; /* [31:25] */
        unsigned int    msi_pvm_enable      : 1  ; /* [24] */
        unsigned int    msi_64bit_enable    : 1  ; /* [23] */
        unsigned int    msi_mult_msg_enable : 3  ; /* [22:20] */
        unsigned int    msi_mult_msg_cap    : 3  ; /* [19:17] */
        unsigned int    msi_enable          : 1  ; /* [16] */
        unsigned int    msi_next_cap_addr   : 8  ; /* [15:8] */
        unsigned int    msi_cap_id          : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MSI_CAP_HEADER;

/* Define the union U_MSI_LADDR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    msi_laddr : 30  ; /* [31:2] */
        unsigned int    rsv_31    : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MSI_LADDR;

/* Define the union U_MSI_HADDR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    msi_uaddr : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MSI_HADDR;

/* Define the union U_MSI_DATA */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_32   : 16  ; /* [31:16] */
        unsigned int    msi_data : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MSI_DATA;

/* Define the union U_MSI_MASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    msi_mask : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MSI_MASK;

/* Define the union U_MSI_PENDING */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    msi_pending : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_MSI_PENDING;

/* Define the union U_PME_CAP_HEADER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    pme_support            : 5  ; /* [31:27] */
        unsigned int    d2_support             : 1  ; /* [26] */
        unsigned int    d1_support             : 1  ; /* [25] */
        unsigned int    aux_current            : 3  ; /* [24:22] */
        unsigned int    device_spec_ini        : 1  ; /* [21] */
        unsigned int    immediate_rn_return_d0 : 1  ; /* [20] */
        unsigned int    pme_clk                : 1  ; /* [19] */
        unsigned int    pme_vesion             : 3  ; /* [18:16] */
        unsigned int    pwr_next_ptr           : 8  ; /* [15:8] */
        unsigned int    pwr_capability_id      : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PME_CAP_HEADER;

/* Define the union U_PME_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    pme_data      : 8  ; /* [31:24] */
        unsigned int    bpcc_en       : 1  ; /* [23] */
        unsigned int    b2_b3_n       : 1  ; /* [22] */
        unsigned int    rsv_33        : 6  ; /* [21:16] */
        unsigned int    pme_status    : 1  ; /* [15] */
        unsigned int    data_scale    : 2  ; /* [14:13] */
        unsigned int    data_sel      : 4  ; /* [12:9] */
        unsigned int    pme_en        : 1  ; /* [8] */
        unsigned int    rsv_34        : 4  ; /* [7:4] */
        unsigned int    no_soft_reset : 1  ; /* [3] */
        unsigned int    rsv_35        : 1  ; /* [2] */
        unsigned int    pwr_status    : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_PME_STATUS;

/* Define the union U_SID_CAP_HEADER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_36            : 16  ; /* [31:16] */
        unsigned int    sid_next_cap_addr : 8  ; /* [15:8] */
        unsigned int    sid_cap_id        : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SID_CAP_HEADER;

/* Define the union U_SSVID_SSID */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    ssid  : 16  ; /* [31:16] */
        unsigned int    ssvid : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SSVID_SSID;

/* Define the union U_AER_CAP_HEADER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    aer_next_cap_addr    : 12  ; /* [31:20] */
        unsigned int    aercapabilityversion : 4  ; /* [19:16] */
        unsigned int    aercapabilityid      : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_AER_CAP_HEADER;

/* Define the union U_UNCR_ERR_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_37                         : 5  ; /* [31:27] */
        unsigned int    poisoned_tlp_egress_blk_err_st : 1  ; /* [26] */
        unsigned int    tlp_pfx_blk_err_st             : 1  ; /* [25] */
        unsigned int    atomicop_eg_blk_st             : 1  ; /* [24] */
        unsigned int    mc_blk_st                      : 1  ; /* [23] */
        unsigned int    uncor_int_err_st               : 1  ; /* [22] */
        unsigned int    acs_vio_st                     : 1  ; /* [21] */
        unsigned int    ur_err_st                      : 1  ; /* [20] */
        unsigned int    ecrc_err_st                    : 1  ; /* [19] */
        unsigned int    mal_tlp_st                     : 1  ; /* [18] */
        unsigned int    rcv_overflow_st                : 1  ; /* [17] */
        unsigned int    unexp_cpl_st                   : 1  ; /* [16] */
        unsigned int    cpl_abort_st                   : 1  ; /* [15] */
        unsigned int    cpl_timeeout_st                : 1  ; /* [14] */
        unsigned int    fc_protocol_err_st             : 1  ; /* [13] */
        unsigned int    poisoned_tlp_st                : 1  ; /* [12] */
        unsigned int    rsv_38                         : 6  ; /* [11:6] */
        unsigned int    sur_down_err_st                : 1  ; /* [5] */
        unsigned int    dl_protocal_err_st             : 1  ; /* [4] */
        unsigned int    rsv_39                         : 3  ; /* [3:1] */
        unsigned int    undefined_4                    : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_UNCR_ERR_STATUS;

/* Define the union U_UNCR_ERR_MASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_40                           : 5  ; /* [31:27] */
        unsigned int    poisoned_tlp_egress_blk_err_mask : 1  ; /* [26] */
        unsigned int    tlp_pfx_blk_err_mask             : 1  ; /* [25] */
        unsigned int    atomicop_eg_blk_mask             : 1  ; /* [24] */
        unsigned int    mc_blk_mask                      : 1  ; /* [23] */
        unsigned int    uncor_int_err_mask               : 1  ; /* [22] */
        unsigned int    acs_vio_mask                     : 1  ; /* [21] */
        unsigned int    ur_err_mask                      : 1  ; /* [20] */
        unsigned int    ecrc_err_mask                    : 1  ; /* [19] */
        unsigned int    mal_tlp_mask                     : 1  ; /* [18] */
        unsigned int    rcv_overflow_mask                : 1  ; /* [17] */
        unsigned int    unexp_cpl_mask                   : 1  ; /* [16] */
        unsigned int    cpl_abort_mask                   : 1  ; /* [15] */
        unsigned int    cpl_timeeout_mask                : 1  ; /* [14] */
        unsigned int    fc_protocol_err_mask             : 1  ; /* [13] */
        unsigned int    poisoned_tlp_mask                : 1  ; /* [12] */
        unsigned int    rsv_41                           : 6  ; /* [11:6] */
        unsigned int    sur_down_err_mask                : 1  ; /* [5] */
        unsigned int    dl_protocal_err_mask             : 1  ; /* [4] */
        unsigned int    rsv_42                           : 3  ; /* [3:1] */
        unsigned int    undefined_8                      : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_UNCR_ERR_MASK;

/* Define the union U_UNCR_ERR_SEVERITY */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_43                          : 5  ; /* [31:27] */
        unsigned int    poisoned_tlp_egress_blk_err_ser : 1  ; /* [26] */
        unsigned int    tlp_pfx_blk_err_ser             : 1  ; /* [25] */
        unsigned int    atomicop_eg_blk_ser             : 1  ; /* [24] */
        unsigned int    mc_blk_ser                      : 1  ; /* [23] */
        unsigned int    uncor_int_err_ser               : 1  ; /* [22] */
        unsigned int    acs_vio_ser                     : 1  ; /* [21] */
        unsigned int    ur_err_ser                      : 1  ; /* [20] */
        unsigned int    ecrc_err_ser                    : 1  ; /* [19] */
        unsigned int    mal_tlp_ser                     : 1  ; /* [18] */
        unsigned int    rcv_overflow_ser                : 1  ; /* [17] */
        unsigned int    unexp_cpl_ser                   : 1  ; /* [16] */
        unsigned int    cpl_abort_ser                   : 1  ; /* [15] */
        unsigned int    cpl_timeeout_ser                : 1  ; /* [14] */
        unsigned int    fc_protocol_err_ser             : 1  ; /* [13] */
        unsigned int    poisoned_tlp_ser                : 1  ; /* [12] */
        unsigned int    rsv_44                          : 6  ; /* [11:6] */
        unsigned int    sur_down_err_ser                : 1  ; /* [5] */
        unsigned int    dl_protocal_err_ser             : 1  ; /* [4] */
        unsigned int    rsv_45                          : 3  ; /* [3:1] */
        unsigned int    undefined_c                     : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_UNCR_ERR_SEVERITY;

/* Define the union U_COR_ERR_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_46                    : 16  ; /* [31:16] */
        unsigned int    header_log_overflow_st    : 1  ; /* [15] */
        unsigned int    cor_int_err_st            : 1  ; /* [14] */
        unsigned int    advisory_non_fatal_err_st : 1  ; /* [13] */
        unsigned int    reply_timer_timout_st     : 1  ; /* [12] */
        unsigned int    rsv_47                    : 3  ; /* [11:9] */
        unsigned int    reply_num_rollover_st     : 1  ; /* [8] */
        unsigned int    bad_dllp_st               : 1  ; /* [7] */
        unsigned int    bad_tlp_st                : 1  ; /* [6] */
        unsigned int    rsv_48                    : 5  ; /* [5:1] */
        unsigned int    rx_err_st                 : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_COR_ERR_STATUS;

/* Define the union U_COR_ERR_MASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_49                      : 16  ; /* [31:16] */
        unsigned int    header_log_overflow_mask    : 1  ; /* [15] */
        unsigned int    cor_int_err_mask            : 1  ; /* [14] */
        unsigned int    advisory_non_fatal_err_mask : 1  ; /* [13] */
        unsigned int    reply_timer_timout_mask     : 1  ; /* [12] */
        unsigned int    rsv_50                      : 3  ; /* [11:9] */
        unsigned int    reply_num_rollover_mask     : 1  ; /* [8] */
        unsigned int    bad_dllp_mask               : 1  ; /* [7] */
        unsigned int    bad_tlp_mask                : 1  ; /* [6] */
        unsigned int    rsv_51                      : 5  ; /* [5:1] */
        unsigned int    rx_err_mask                 : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_COR_ERR_MASK;

/* Define the union U_ADVACD_CAP_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_52               : 19  ; /* [31:13] */
        unsigned int    cmp_timeout_log_cap  : 1  ; /* [12] */
        unsigned int    tlp_prefix_log_pre   : 1  ; /* [11] */
        unsigned int    multi_hdr_rec_enable : 1  ; /* [10] */
        unsigned int    multi_hdr_rec_cap    : 1  ; /* [9] */
        unsigned int    ecrc_check_en        : 1  ; /* [8] */
        unsigned int    ecrc_check_cap       : 1  ; /* [7] */
        unsigned int    ecrc_gen_en          : 1  ; /* [6] */
        unsigned int    ecrc_gen_cap         : 1  ; /* [5] */
        unsigned int    first_err_ptr        : 5  ; /* [4:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_ADVACD_CAP_CTRL;

/* Define the union U_FIRST_HEADER_LOG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    first_header_log : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_FIRST_HEADER_LOG;

/* Define the union U_SECOND_HEADER_LOG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    second_header_log : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SECOND_HEADER_LOG;

/* Define the union U_THIRD_HEADER_LOG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    third_header_log : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_THIRD_HEADER_LOG;

/* Define the union U_FOUR_HEADER_LOG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    four_header_log : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_FOUR_HEADER_LOG;

/* Define the union U_ROOT_ERROR_COMMAND */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_53           : 29  ; /* [31:3] */
        unsigned int    fatal_err_en     : 1  ; /* [2] */
        unsigned int    non_fatal_err_en : 1  ; /* [1] */
        unsigned int    cor_err_en       : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_ROOT_ERROR_COMMAND;

/* Define the union U_ROOT_ERROR_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    aer_int_number      : 5  ; /* [31:27] */
        unsigned int    rsv_54              : 20  ; /* [26:7] */
        unsigned int    fatal_msg_rcv       : 1  ; /* [6] */
        unsigned int    non_fatal_msg_rcv   : 1  ; /* [5] */
        unsigned int    first_uncor_err     : 1  ; /* [4] */
        unsigned int    multi_uncor_err_rcv : 1  ; /* [3] */
        unsigned int    uncor_err_rcv       : 1  ; /* [2] */
        unsigned int    multi_cor_err_rcv   : 1  ; /* [1] */
        unsigned int    core_err_rcv        : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_ROOT_ERROR_STATUS;

/* Define the union U_ERR_SOURCE_IDEN */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    err_non_cir_source : 16  ; /* [31:16] */
        unsigned int    err_cor_source     : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_ERR_SOURCE_IDEN;

/* Define the union U_FIRST_PREFIX_LOG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    first_prefix_log : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_FIRST_PREFIX_LOG;

/* Define the union U_SECOND_PREFIX_LOG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    second_prefix_log : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SECOND_PREFIX_LOG;

/* Define the union U_THIRD_PREFIX_LOG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    third_prefix_log : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_THIRD_PREFIX_LOG;

/* Define the union U_FOUR_PREFIX_LOG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    four_prefix_log : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_FOUR_PREFIX_LOG;

/* Define the union U_TPH_EXTEND_CAP */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    tph_next_cap_offset : 12  ; /* [31:20] */
        unsigned int    tph_cap_version     : 4  ; /* [19:16] */
        unsigned int    tph_extend_cap_id   : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_TPH_EXTEND_CAP;

/* Define the union U_TPH_REQ_CAP */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_55                  : 5  ; /* [31:27] */
        unsigned int    st_table_size           : 11  ; /* [26:16] */
        unsigned int    rsv_56                  : 5  ; /* [15:11] */
        unsigned int    st_table_location       : 2  ; /* [10:9] */
        unsigned int    extend_tph_req_support  : 1  ; /* [8] */
        unsigned int    rsv_57                  : 5  ; /* [7:3] */
        unsigned int    device_spc_mode_support : 1  ; /* [2] */
        unsigned int    int_vector_mode_support : 1  ; /* [1] */
        unsigned int    no_st_mode_support      : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_TPH_REQ_CAP;

/* Define the union U_TPH_REQ_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_58         : 22  ; /* [31:10] */
        unsigned int    tph_req_enable : 2  ; /* [9:8] */
        unsigned int    rsv_59         : 5  ; /* [7:3] */
        unsigned int    st_mode_sel    : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_TPH_REQ_CTRL;

/* Define the union U_SECONDARY_PCIE_EXT_CAP_HED */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sec_pcie_next_cap_offset : 12  ; /* [31:20] */
        unsigned int    sec_pcie_cap_version     : 4  ; /* [19:16] */
        unsigned int    sec_pcie_ext_cap_id      : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SECONDARY_PCIE_EXT_CAP_HED;

/* Define the union U_LINK_CONTROL3_REGISTER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_60                           : 16  ; /* [31:16] */
        unsigned int    sec_pcie_lower_skp_en            : 7  ; /* [15:9] */
        unsigned int    rsv_61                           : 7  ; /* [8:2] */
        unsigned int    sec_pcie_link_equaliz_req_int_en : 1  ; /* [1] */
        unsigned int    sec_pcie_perform_equaliz         : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_LINK_CONTROL3_REGISTER;

/* Define the union U_LANE_ERROR_STATUS_REG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_62                  : 16  ; /* [31:16] */
        unsigned int    sec_pcie_lane_err_staus : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_LANE_ERROR_STATUS_REG;

/* Define the union U_LINK_CONTROL3_REGISTER01 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_63                            : 1  ; /* [31] */
        unsigned int    sec_pcie_8g_ln1_up_rx_preset_hint : 3  ; /* [30:28] */
        unsigned int    sec_pcie_8g_ln1_up_tx_preset      : 4  ; /* [27:24] */
        unsigned int    rsv_64                            : 1  ; /* [23] */
        unsigned int    sec_pcie_8g_ln1_dp_rx_preset_hint : 3  ; /* [22:20] */
        unsigned int    sec_pcie_8g_ln1_dp_tx_preset      : 4  ; /* [19:16] */
        unsigned int    rsv_65                            : 1  ; /* [15] */
        unsigned int    sec_pcie_8g_ln0_up_rx_preset_hint : 3  ; /* [14:12] */
        unsigned int    sec_pcie_8g_ln0_up_tx_preset      : 4  ; /* [11:8] */
        unsigned int    rsv_66                            : 1  ; /* [7] */
        unsigned int    sec_pcie_8g_ln0_dp_rx_preset_hint : 3  ; /* [6:4] */
        unsigned int    sec_pcie_8g_ln0_dp_tx_preset      : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_LINK_CONTROL3_REGISTER01;

/* Define the union U_LINK_CONTROL3_REGISTER23 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_67                            : 1  ; /* [31] */
        unsigned int    sec_pcie_8g_ln3_up_rx_preset_hint : 3  ; /* [30:28] */
        unsigned int    sec_pcie_8g_ln3_up_tx_preset      : 4  ; /* [27:24] */
        unsigned int    rsv_68                            : 1  ; /* [23] */
        unsigned int    sec_pcie_8g_ln3_dp_rx_preset_hint : 3  ; /* [22:20] */
        unsigned int    sec_pcie_8g_ln3_dp_tx_preset      : 4  ; /* [19:16] */
        unsigned int    rsv_69                            : 1  ; /* [15] */
        unsigned int    sec_pcie_8g_ln2_up_rx_preset_hint : 3  ; /* [14:12] */
        unsigned int    sec_pcie_8g_ln2_up_tx_preset      : 4  ; /* [11:8] */
        unsigned int    rsv_70                            : 1  ; /* [7] */
        unsigned int    sec_pcie_8g_ln2_dp_rx_preset_hint : 3  ; /* [6:4] */
        unsigned int    sec_pcie_8g_ln2_dp_tx_preset      : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_LINK_CONTROL3_REGISTER23;

/* Define the union U_LINK_CONTROL3_REGISTER45 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_71                            : 1  ; /* [31] */
        unsigned int    sec_pcie_8g_ln5_up_rx_preset_hint : 3  ; /* [30:28] */
        unsigned int    sec_pcie_8g_ln5_up_tx_preset      : 4  ; /* [27:24] */
        unsigned int    rsv_72                            : 1  ; /* [23] */
        unsigned int    sec_pcie_8g_ln5_dp_rx_preset_hint : 3  ; /* [22:20] */
        unsigned int    sec_pcie_8g_ln5_dp_tx_preset      : 4  ; /* [19:16] */
        unsigned int    rsv_73                            : 1  ; /* [15] */
        unsigned int    sec_pcie_8g_ln4_up_rx_preset_hint : 3  ; /* [14:12] */
        unsigned int    sec_pcie_8g_ln4_up_tx_preset      : 4  ; /* [11:8] */
        unsigned int    rsv_74                            : 1  ; /* [7] */
        unsigned int    sec_pcie_8g_ln4_dp_rx_preset_hint : 3  ; /* [6:4] */
        unsigned int    sec_pcie_8g_ln4_dp_tx_preset      : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_LINK_CONTROL3_REGISTER45;

/* Define the union U_LINK_CONTROL3_REGISTER67 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_75                            : 1  ; /* [31] */
        unsigned int    sec_pcie_8g_ln7_up_rx_preset_hint : 3  ; /* [30:28] */
        unsigned int    sec_pcie_8g_ln7_up_tx_preset      : 4  ; /* [27:24] */
        unsigned int    rsv_76                            : 1  ; /* [23] */
        unsigned int    sec_pcie_8g_ln7_dp_rx_preset_hint : 3  ; /* [22:20] */
        unsigned int    sec_pcie_8g_ln7_dp_tx_preset      : 4  ; /* [19:16] */
        unsigned int    rsv_77                            : 1  ; /* [15] */
        unsigned int    sec_pcie_8g_ln6_up_rx_preset_hint : 3  ; /* [14:12] */
        unsigned int    sec_pcie_8g_ln6_up_tx_preset      : 4  ; /* [11:8] */
        unsigned int    rsv_78                            : 1  ; /* [7] */
        unsigned int    sec_pcie_8g_ln6_dp_rx_preset_hint : 3  ; /* [6:4] */
        unsigned int    sec_pcie_8g_ln6_dp_tx_preset      : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_LINK_CONTROL3_REGISTER67;

/* Define the union U_LINK_CONTROL3_REGISTER89 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_79                            : 1  ; /* [31] */
        unsigned int    sec_pcie_8g_ln9_up_rx_preset_hint : 3  ; /* [30:28] */
        unsigned int    sec_pcie_8g_ln9_up_tx_preset      : 4  ; /* [27:24] */
        unsigned int    rsv_80                            : 1  ; /* [23] */
        unsigned int    sec_pcie_8g_ln9_dp_rx_preset_hint : 3  ; /* [22:20] */
        unsigned int    sec_pcie_8g_ln9_dp_tx_preset      : 4  ; /* [19:16] */
        unsigned int    rsv_81                            : 1  ; /* [15] */
        unsigned int    sec_pcie_8g_ln8_up_rx_preset_hint : 3  ; /* [14:12] */
        unsigned int    sec_pcie_8g_ln8_up_tx_preset      : 4  ; /* [11:8] */
        unsigned int    rsv_82                            : 1  ; /* [7] */
        unsigned int    sec_pcie_8g_ln8_dp_rx_preset_hint : 3  ; /* [6:4] */
        unsigned int    sec_pcie_8g_ln8_dp_tx_preset      : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_LINK_CONTROL3_REGISTER89;

/* Define the union U_LINK_CONTROL3_REGISTER1011 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_83                             : 1  ; /* [31] */
        unsigned int    sec_pcie_8g_ln11_up_rx_preset_hint : 3  ; /* [30:28] */
        unsigned int    sec_pcie_8g_ln11_up_tx_preset      : 4  ; /* [27:24] */
        unsigned int    rsv_84                             : 1  ; /* [23] */
        unsigned int    sec_pcie_8g_ln11_dp_rx_preset_hint : 3  ; /* [22:20] */
        unsigned int    sec_pcie_8g_ln11_dp_tx_preset      : 4  ; /* [19:16] */
        unsigned int    rsv_85                             : 1  ; /* [15] */
        unsigned int    sec_pcie_8g_ln10_up_rx_preset_hint : 3  ; /* [14:12] */
        unsigned int    sec_pcie_8g_ln10_up_tx_preset      : 4  ; /* [11:8] */
        unsigned int    rsv_86                             : 1  ; /* [7] */
        unsigned int    sec_pcie_8g_ln10_dp_rx_preset_hint : 3  ; /* [6:4] */
        unsigned int    sec_pcie_8g_ln10_dp_tx_preset      : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_LINK_CONTROL3_REGISTER1011;

/* Define the union U_LINK_CONTROL3_REGISTER1213 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_87                             : 1  ; /* [31] */
        unsigned int    sec_pcie_8g_ln13_up_rx_preset_hint : 3  ; /* [30:28] */
        unsigned int    sec_pcie_8g_ln13_up_tx_preset      : 4  ; /* [27:24] */
        unsigned int    rsv_88                             : 1  ; /* [23] */
        unsigned int    sec_pcie_8g_ln13_dp_rx_preset_hint : 3  ; /* [22:20] */
        unsigned int    sec_pcie_8g_ln13_dp_tx_preset      : 4  ; /* [19:16] */
        unsigned int    rsv_89                             : 1  ; /* [15] */
        unsigned int    sec_pcie_8g_ln12_up_rx_preset_hint : 3  ; /* [14:12] */
        unsigned int    sec_pcie_8g_ln12_up_tx_preset      : 4  ; /* [11:8] */
        unsigned int    rsv_90                             : 1  ; /* [7] */
        unsigned int    sec_pcie_8g_ln12_dp_rx_preset_hint : 3  ; /* [6:4] */
        unsigned int    sec_pcie_8g_ln12_dp_tx_preset      : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_LINK_CONTROL3_REGISTER1213;

/* Define the union U_LINK_CONTROL3_REGISTER1415 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_91                             : 1  ; /* [31] */
        unsigned int    sec_pcie_8g_ln15_up_rx_preset_hint : 3  ; /* [30:28] */
        unsigned int    sec_pcie_8g_ln15_up_tx_preset      : 4  ; /* [27:24] */
        unsigned int    rsv_92                             : 1  ; /* [23] */
        unsigned int    sec_pcie_8g_ln15_dp_rx_preset_hint : 3  ; /* [22:20] */
        unsigned int    sec_pcie_8g_ln15_dp_tx_preset      : 4  ; /* [19:16] */
        unsigned int    rsv_93                             : 1  ; /* [15] */
        unsigned int    sec_pcie_8g_ln14_up_rx_preset_hint : 3  ; /* [14:12] */
        unsigned int    sec_pcie_8g_ln14_up_tx_preset      : 4  ; /* [11:8] */
        unsigned int    rsv_94                             : 1  ; /* [7] */
        unsigned int    sec_pcie_8g_ln14_dp_rx_preset_hint : 3  ; /* [6:4] */
        unsigned int    sec_pcie_8g_ln14_dp_tx_preset      : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_LINK_CONTROL3_REGISTER1415;

/* Define the union U_VC_CAP_0X00 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    vc_next_cap_offset : 12  ; /* [31:20] */
        unsigned int    vc_cap_version     : 4  ; /* [19:16] */
        unsigned int    vc_cap_id          : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VC_CAP_0X00;

/* Define the union U_VC_CAP_0X04 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_95                  : 20  ; /* [31:12] */
        unsigned int    vc_func_arb_table_size  : 2  ; /* [11:10] */
        unsigned int    vc_ref_clk              : 2  ; /* [9:8] */
        unsigned int    rsv_96                  : 1  ; /* [7] */
        unsigned int    vc_low_pri_ext_vc_count : 3  ; /* [6:4] */
        unsigned int    rsv_97                  : 1  ; /* [3] */
        unsigned int    vc_ext_vc_count         : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VC_CAP_0X04;

/* Define the union U_VC_CAP_0X08 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    vc_vc_arb_table_offset : 8  ; /* [31:24] */
        unsigned int    rsv_98                 : 16  ; /* [23:8] */
        unsigned int    vc_vc_arb_cap          : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VC_CAP_0X08;

/* Define the union U_VC_CAP_0X0C */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_99               : 15  ; /* [31:17] */
        unsigned int    vc_vc_table_status   : 1  ; /* [16] */
        unsigned int    rsv_100              : 12  ; /* [15:4] */
        unsigned int    vc_vc_arb_sel        : 3  ; /* [3:1] */
        unsigned int    vc_load_vc_arb_table : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VC_CAP_0X0C;

/* Define the union U_VC_CAP_0X10 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    vc0_port_arb_table_offset : 8  ; /* [31:24] */
        unsigned int    rsv_101                   : 1  ; /* [23] */
        unsigned int    vc0_max_time_slot         : 7  ; /* [22:16] */
        unsigned int    vc0_reject_snoop_trs      : 1  ; /* [15] */
        unsigned int    vc10_undefined            : 1  ; /* [14] */
        unsigned int    rsv_102                   : 6  ; /* [13:8] */
        unsigned int    vc0_port_arb_cap          : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VC_CAP_0X10;

/* Define the union U_VC_CAP_0X14 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    vc0_enable              : 1  ; /* [31] */
        unsigned int    rsv_103                 : 4  ; /* [30:27] */
        unsigned int    vc0_vc_id               : 3  ; /* [26:24] */
        unsigned int    rsv_104                 : 4  ; /* [23:20] */
        unsigned int    vc0_port_arb_sel        : 3  ; /* [19:17] */
        unsigned int    vc0_load_port_arb_table : 1  ; /* [16] */
        unsigned int    rsv_105                 : 8  ; /* [15:8] */
        unsigned int    vc0_tc_vc_map           : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VC_CAP_0X14;

/* Define the union U_VC_CAP_0X18 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_106                   : 14  ; /* [31:18] */
        unsigned int    vc0_negoti_pending        : 1  ; /* [17] */
        unsigned int    vc0_port_arb_table_status : 1  ; /* [16] */
        unsigned int    rsv_107                   : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VC_CAP_0X18;

/* Define the union U_VC_CAP_0X1C */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    vc1_port_arb_table_offset : 8  ; /* [31:24] */
        unsigned int    rsv_108                   : 1  ; /* [23] */
        unsigned int    vc1_max_time_slot         : 7  ; /* [22:16] */
        unsigned int    vc1_reject_snoop_trs      : 1  ; /* [15] */
        unsigned int    vc1c_undefined            : 1  ; /* [14] */
        unsigned int    rsv_109                   : 6  ; /* [13:8] */
        unsigned int    vc1_port_arb_cap          : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VC_CAP_0X1C;

/* Define the union U_VC_CAP_0X20 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    vc1_enable              : 1  ; /* [31] */
        unsigned int    rsv_110                 : 4  ; /* [30:27] */
        unsigned int    vc1_vc_id               : 3  ; /* [26:24] */
        unsigned int    rsv_111                 : 4  ; /* [23:20] */
        unsigned int    vc1_port_arb_sel        : 3  ; /* [19:17] */
        unsigned int    vc1_load_port_arb_table : 1  ; /* [16] */
        unsigned int    rsv_112                 : 8  ; /* [15:8] */
        unsigned int    vc1_tc_vc_map           : 8  ; /* [7:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VC_CAP_0X20;

/* Define the union U_VC_CAP_0X24 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_113                   : 14  ; /* [31:18] */
        unsigned int    vc1_negoti_pending        : 1  ; /* [17] */
        unsigned int    vc1_port_arb_table_status : 1  ; /* [16] */
        unsigned int    rsv_114                   : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VC_CAP_0X24;

/* Define the union U_DEVICE_SERIAL_NUMBER_CAP_HEADER */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dsn_next_cap_offset : 12  ; /* [31:20] */
        unsigned int    dsn_cap_version     : 4  ; /* [19:16] */
        unsigned int    dsn_extend_cap      : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DEVICE_SERIAL_NUMBER_CAP_HEADER;

/* Define the union U_SERIAL_LNUM */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dsn_1st_dw : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SERIAL_LNUM;

/* Define the union U_SERIAL_HNUM */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dsn_2nd_dw : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_SERIAL_HNUM;

/* Define the union U_ACS_CAP_0X00 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    acs_cap_next_cap_addr : 12  ; /* [31:20] */
        unsigned int    acs_cap_version       : 4  ; /* [19:16] */
        unsigned int    acs_capid             : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_ACS_CAP_0X00;

/* Define the union U_ACS_CAP_0X04 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_115                 : 9  ; /* [31:23] */
        unsigned int    acs_direct_tx_p2p_en    : 1  ; /* [22] */
        unsigned int    acs_p2p_egress_ctrl_en  : 1  ; /* [21] */
        unsigned int    acs_up_forward_en       : 1  ; /* [20] */
        unsigned int    acs_p2p_cpl_redirect_en : 1  ; /* [19] */
        unsigned int    acs_p2p_req_redirect_en : 1  ; /* [18] */
        unsigned int    acs_tx_block_en         : 1  ; /* [17] */
        unsigned int    acs_src_vld_en          : 1  ; /* [16] */
        unsigned int    acs_ctrl_vec_size       : 8  ; /* [15:8] */
        unsigned int    rsv_116                 : 1  ; /* [7] */
        unsigned int    acs_direct_tx_p2p       : 1  ; /* [6] */
        unsigned int    acs_p2p_egress_ctrl     : 1  ; /* [5] */
        unsigned int    acs_up_forward          : 1  ; /* [4] */
        unsigned int    acs_p2p_cpl_redirect    : 1  ; /* [3] */
        unsigned int    acs_p2p_req_redirect    : 1  ; /* [2] */
        unsigned int    acs_tx_block            : 1  ; /* [1] */
        unsigned int    acs_src_vld             : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_ACS_CAP_0X04;

/* Define the union U_DPC_CAP_0X00 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dpc_next_offset : 12  ; /* [31:20] */
        unsigned int    dpc_cap_ver     : 4  ; /* [19:16] */
        unsigned int    dpc_cap_id      : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X00;

/* Define the union U_DPC_CAP_0X04 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_117                 : 8  ; /* [31:24] */
        unsigned int    dl_active_err_cor_en    : 1  ; /* [23] */
        unsigned int    dpc_soft_trig           : 1  ; /* [22] */
        unsigned int    ep_egress_blk_en        : 1  ; /* [21] */
        unsigned int    dpc_err_cor_en          : 1  ; /* [20] */
        unsigned int    dpc_int_en              : 1  ; /* [19] */
        unsigned int    dpc_cpl_ctrl            : 1  ; /* [18] */
        unsigned int    dp_trig_en              : 2  ; /* [17:16] */
        unsigned int    rsv_118                 : 3  ; /* [15:13] */
        unsigned int    dl_active_signal_sup    : 1  ; /* [12] */
        unsigned int    pio_log_size            : 4  ; /* [11:8] */
        unsigned int    soft_trig_sup           : 1  ; /* [7] */
        unsigned int    egress_block_ep_tlp_sup : 1  ; /* [6] */
        unsigned int    ext_for_dpc             : 1  ; /* [5] */
        unsigned int    dcp_int_msg_num         : 5  ; /* [4:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X04;

/* Define the union U_DPC_CAP_0X08 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dpc_err_src_id      : 16  ; /* [31:16] */
        unsigned int    rsv_119             : 3  ; /* [15:13] */
        unsigned int    rp_pio_1st_ptr      : 5  ; /* [12:8] */
        unsigned int    rsv_120             : 1  ; /* [7] */
        unsigned int    dpc_trig_reason_ext : 2  ; /* [6:5] */
        unsigned int    dpc_rp_busy         : 1  ; /* [4] */
        unsigned int    dpc_int_sts         : 1  ; /* [3] */
        unsigned int    dpc_trig_reason     : 2  ; /* [2:1] */
        unsigned int    dpc_trig_sts        : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X08;

/* Define the union U_DPC_CAP_0X0C */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_121 : 13  ; /* [31:19] */
        unsigned int    mem_cto : 1  ; /* [18] */
        unsigned int    mem_ca  : 1  ; /* [17] */
        unsigned int    mem_ur  : 1  ; /* [16] */
        unsigned int    rsv_122 : 5  ; /* [15:11] */
        unsigned int    io_cto  : 1  ; /* [10] */
        unsigned int    io_ca   : 1  ; /* [9] */
        unsigned int    io_ur   : 1  ; /* [8] */
        unsigned int    rsv_123 : 5  ; /* [7:3] */
        unsigned int    cfg_cto : 1  ; /* [2] */
        unsigned int    cfg_ca  : 1  ; /* [1] */
        unsigned int    cfg_ur  : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X0C;

/* Define the union U_DPC_CAP_0X10 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_124      : 13  ; /* [31:19] */
        unsigned int    mem_cto_mask : 1  ; /* [18] */
        unsigned int    mem_ca_mask  : 1  ; /* [17] */
        unsigned int    mem_ur_mask  : 1  ; /* [16] */
        unsigned int    rsv_125      : 5  ; /* [15:11] */
        unsigned int    io_cto_mask  : 1  ; /* [10] */
        unsigned int    io_ca_mask   : 1  ; /* [9] */
        unsigned int    io_ur_mask   : 1  ; /* [8] */
        unsigned int    rsv_126      : 5  ; /* [7:3] */
        unsigned int    cfg_cto_mask : 1  ; /* [2] */
        unsigned int    cfg_ca_mask  : 1  ; /* [1] */
        unsigned int    cfg_ur_mask  : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X10;

/* Define the union U_DPC_CAP_0X14 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_127     : 13  ; /* [31:19] */
        unsigned int    mem_cto_svr : 1  ; /* [18] */
        unsigned int    mem_ca_svr  : 1  ; /* [17] */
        unsigned int    mem_ur_svr  : 1  ; /* [16] */
        unsigned int    rsv_128     : 5  ; /* [15:11] */
        unsigned int    io_cto_svr  : 1  ; /* [10] */
        unsigned int    io_ca_svr   : 1  ; /* [9] */
        unsigned int    io_ur_svr   : 1  ; /* [8] */
        unsigned int    rsv_129     : 5  ; /* [7:3] */
        unsigned int    cfg_cto_svr : 1  ; /* [2] */
        unsigned int    cfg_ca_svr  : 1  ; /* [1] */
        unsigned int    cfg_ur_svr  : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X14;

/* Define the union U_DPC_CAP_0X18 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_130        : 13  ; /* [31:19] */
        unsigned int    mem_cto_syserr : 1  ; /* [18] */
        unsigned int    mem_ca_syserr  : 1  ; /* [17] */
        unsigned int    mem_ur_syserr  : 1  ; /* [16] */
        unsigned int    rsv_131        : 5  ; /* [15:11] */
        unsigned int    io_cto_syserr  : 1  ; /* [10] */
        unsigned int    io_ca_syserr   : 1  ; /* [9] */
        unsigned int    io_ur_syserr   : 1  ; /* [8] */
        unsigned int    rsv_132        : 5  ; /* [7:3] */
        unsigned int    cfg_cto_syserr : 1  ; /* [2] */
        unsigned int    cfg_ca_syserr  : 1  ; /* [1] */
        unsigned int    cfg_ur_syserr  : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X18;

/* Define the union U_DPC_CAP_0X1C */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_133           : 13  ; /* [31:19] */
        unsigned int    mem_cto_exception : 1  ; /* [18] */
        unsigned int    mem_ca_exception  : 1  ; /* [17] */
        unsigned int    mem_ur_exception  : 1  ; /* [16] */
        unsigned int    rsv_134           : 5  ; /* [15:11] */
        unsigned int    io_cto_exception  : 1  ; /* [10] */
        unsigned int    io_ca_exception   : 1  ; /* [9] */
        unsigned int    io_ur_exception   : 1  ; /* [8] */
        unsigned int    rsv_135           : 5  ; /* [7:3] */
        unsigned int    cfg_cto_exception : 1  ; /* [2] */
        unsigned int    cfg_ca_exception  : 1  ; /* [1] */
        unsigned int    cfg_ur_exception  : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X1C;

/* Define the union U_DPC_CAP_0X20 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    log_hed_dw1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X20;

/* Define the union U_DPC_CAP_0X24 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    log_hed_dw2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X24;

/* Define the union U_DPC_CAP_0X28 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    log_hed_dw3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X28;

/* Define the union U_DPC_CAP_0X2C */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    log_hed_dw4 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X2C;

/* Define the union U_DPC_CAP_0X30 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    imspcec_log : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X30;

/* Define the union U_DPC_CAP_0X34 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    prefix_log_dw1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X34;

/* Define the union U_DPC_CAP_0X38 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    prefix_log_dw2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X38;

/* Define the union U_DPC_CAP_0X3C */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    prefix_log_dw3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X3C;

/* Define the union U_DPC_CAP_0X40 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    prefix_log_dw4 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DPC_CAP_0X40;

/* Define the union U_DL_FEATURE_CAP_REG00 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dl_feature_cap_next_cap_addr : 12  ; /* [31:20] */
        unsigned int    dl_feature_cap_version       : 4  ; /* [19:16] */
        unsigned int    dl_feature_capid             : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DL_FEATURE_CAP_REG00;

/* Define the union U_DL_FEATURE_CAP_REG04 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    feature_exchange_en          : 1  ; /* [31] */
        unsigned int    rsv_136                      : 8  ; /* [30:23] */
        unsigned int    local_future_feature_support : 22  ; /* [22:1] */
        unsigned int    local_scale_fc_support       : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DL_FEATURE_CAP_REG04;

/* Define the union U_DL_FEATURE_CAP_REG08 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    remote_feature_sup_vld        : 1  ; /* [31] */
        unsigned int    rsv_137                       : 8  ; /* [30:23] */
        unsigned int    remote_future_feature_support : 22  ; /* [22:1] */
        unsigned int    remote_scale_fc_support       : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_DL_FEATURE_CAP_REG08;

/* Define the union U_RXMARGIN_CAP_REG00 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rxmargin_cap_next_cap_addr : 12  ; /* [31:20] */
        unsigned int    rxmargin_cap_version       : 4  ; /* [19:16] */
        unsigned int    rxmargin_capid             : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_RXMARGIN_CAP_REG00;

/* Define the union U_RXMARGIN_CAP_REG04 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_138                : 14  ; /* [31:18] */
        unsigned int    margin_soft_ready      : 1  ; /* [17] */
        unsigned int    margin_ready           : 1  ; /* [16] */
        unsigned int    rsv_139                : 15  ; /* [15:1] */
        unsigned int    margin_use_driver_soft : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_RXMARGIN_CAP_REG04;

/* Define the union U_RXMARGIN_CAP_REG08 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    margin_payload_status : 8  ; /* [31:24] */
        unsigned int    rsvdp_bit23           : 1  ; /* [23] */
        unsigned int    usage_model_status    : 1  ; /* [22] */
        unsigned int    margin_type_status    : 3  ; /* [21:19] */
        unsigned int    receiver_num_status   : 3  ; /* [18:16] */
        unsigned int    margin_payload        : 8  ; /* [15:8] */
        unsigned int    rsvdp_bit7            : 1  ; /* [7] */
        unsigned int    usage_model           : 1  ; /* [6] */
        unsigned int    margin_type           : 3  ; /* [5:3] */
        unsigned int    receiver_num          : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_RXMARGIN_CAP_REG08;

/* Define the union U_CCIX_TS_CAP_REG00 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    ccix_ts_cap_next_cap_addr : 12  ; /* [31:20] */
        unsigned int    ccix_ts_cap_version       : 4  ; /* [19:16] */
        unsigned int    ccix_ts_capid             : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CCIX_TS_CAP_REG00;

/* Define the union U_CCIX_TS_CAP_REG04 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    dvsec_length    : 12  ; /* [31:20] */
        unsigned int    dvsec_version   : 4  ; /* [19:16] */
        unsigned int    dvsec_vendor_id : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CCIX_TS_CAP_REG04;

/* Define the union U_CCIX_TS_CAP_REG08 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_140           : 7  ; /* [31:25] */
        unsigned int    esm_mode_sup      : 1  ; /* [24] */
        unsigned int    esm_cali_done     : 1  ; /* [23] */
        unsigned int    esm_cur_data_rate : 7  ; /* [22:16] */
        unsigned int    dvsec_id          : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CCIX_TS_CAP_REG08;

/* Define the union U_CCIX_TS_CAP_REG0C */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    esm_support_rate : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CCIX_TS_CAP_REG0C;

/* Define the union U_CCIX_TS_CAP_REG10 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_141 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CCIX_TS_CAP_REG10;

/* Define the union U_CCIX_TS_CAP_REG14 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_142        : 16  ; /* [31:16] */
        unsigned int    esm_enable     : 1  ; /* [15] */
        unsigned int    esm_data_rate1 : 7  ; /* [14:8] */
        unsigned int    esm_perform_eq : 1  ; /* [7] */
        unsigned int    esm_data_rate0 : 7  ; /* [6:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CCIX_TS_CAP_REG14;

/* Define the union U_CCIX_TS_CAP_REG18 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    esm_up_20g_txpreset_lane3 : 4  ; /* [31:28] */
        unsigned int    esm_dp_20g_txpreset_lane3 : 4  ; /* [27:24] */
        unsigned int    esm_up_20g_txpreset_lane2 : 4  ; /* [23:20] */
        unsigned int    esm_dp_20g_txpreset_lane2 : 4  ; /* [19:16] */
        unsigned int    esm_up_20g_txpreset_lane1 : 4  ; /* [15:12] */
        unsigned int    esm_dp_20g_txpreset_lane1 : 4  ; /* [11:8] */
        unsigned int    esm_up_20g_txpreset_lane0 : 4  ; /* [7:4] */
        unsigned int    esm_dp_20g_txpreset_lane0 : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CCIX_TS_CAP_REG18;

/* Define the union U_CCIX_TS_CAP_REG1C */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    esm_up_20g_txpreset_lane7 : 4  ; /* [31:28] */
        unsigned int    esm_dp_20g_txpreset_lane7 : 4  ; /* [27:24] */
        unsigned int    esm_up_20g_txpreset_lane6 : 4  ; /* [23:20] */
        unsigned int    esm_dp_20g_txpreset_lane6 : 4  ; /* [19:16] */
        unsigned int    esm_up_20g_txpreset_lane5 : 4  ; /* [15:12] */
        unsigned int    esm_dp_20g_txpreset_lane5 : 4  ; /* [11:8] */
        unsigned int    esm_up_20g_txpreset_lane4 : 4  ; /* [7:4] */
        unsigned int    esm_dp_20g_txpreset_lane4 : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CCIX_TS_CAP_REG1C;

/* Define the union U_CCIX_TS_CAP_REG20 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    esm_up_20g_txpreset_lane11 : 4  ; /* [31:28] */
        unsigned int    esm_dp_20g_txpreset_lane11 : 4  ; /* [27:24] */
        unsigned int    esm_up_20g_txpreset_lane10 : 4  ; /* [23:20] */
        unsigned int    esm_dp_20g_txpreset_lane10 : 4  ; /* [19:16] */
        unsigned int    esm_up_20g_txpreset_lane9  : 4  ; /* [15:12] */
        unsigned int    esm_dp_20g_txpreset_lane9  : 4  ; /* [11:8] */
        unsigned int    esm_up_20g_txpreset_lane8  : 4  ; /* [7:4] */
        unsigned int    esm_dp_20g_txpreset_lane8  : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CCIX_TS_CAP_REG20;

/* Define the union U_CCIX_TS_CAP_REG24 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    esm_up_20g_txpreset_lane15 : 4  ; /* [31:28] */
        unsigned int    esm_dp_20g_txpreset_lane15 : 4  ; /* [27:24] */
        unsigned int    esm_up_20g_txpreset_lane14 : 4  ; /* [23:20] */
        unsigned int    esm_dp_20g_txpreset_lane14 : 4  ; /* [19:16] */
        unsigned int    esm_up_20g_txpreset_lane13 : 4  ; /* [15:12] */
        unsigned int    esm_dp_20g_txpreset_lane13 : 4  ; /* [11:8] */
        unsigned int    esm_up_20g_txpreset_lane12 : 4  ; /* [7:4] */
        unsigned int    esm_dp_20g_txpreset_lane12 : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CCIX_TS_CAP_REG24;

/* Define the union U_CCIX_TS_CAP_REG28 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    esm_up_25g_txpreset_lane3 : 4  ; /* [31:28] */
        unsigned int    esm_dp_25g_txpreset_lane3 : 4  ; /* [27:24] */
        unsigned int    esm_up_25g_txpreset_lane2 : 4  ; /* [23:20] */
        unsigned int    esm_dp_25g_txpreset_lane2 : 4  ; /* [19:16] */
        unsigned int    esm_up_25g_txpreset_lane1 : 4  ; /* [15:12] */
        unsigned int    esm_dp_25g_txpreset_lane1 : 4  ; /* [11:8] */
        unsigned int    esm_up_25g_txpreset_lane0 : 4  ; /* [7:4] */
        unsigned int    esm_dp_25g_txpreset_lane0 : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CCIX_TS_CAP_REG28;

/* Define the union U_CCIX_TS_CAP_REG2C */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    esm_up_25g_txpreset_lane7 : 4  ; /* [31:28] */
        unsigned int    esm_dp_25g_txpreset_lane7 : 4  ; /* [27:24] */
        unsigned int    esm_up_25g_txpreset_lane6 : 4  ; /* [23:20] */
        unsigned int    esm_dp_25g_txpreset_lane6 : 4  ; /* [19:16] */
        unsigned int    esm_up_25g_txpreset_lane5 : 4  ; /* [15:12] */
        unsigned int    esm_dp_25g_txpreset_lane5 : 4  ; /* [11:8] */
        unsigned int    esm_up_25g_txpreset_lane4 : 4  ; /* [7:4] */
        unsigned int    esm_dp_25g_txpreset_lane4 : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CCIX_TS_CAP_REG2C;

/* Define the union U_CCIX_TS_CAP_REG30 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    esm_up_25g_txpreset_lane11 : 4  ; /* [31:28] */
        unsigned int    esm_dp_25g_txpreset_lane11 : 4  ; /* [27:24] */
        unsigned int    esm_up_25g_txpreset_lane10 : 4  ; /* [23:20] */
        unsigned int    esm_dp_25g_txpreset_lane10 : 4  ; /* [19:16] */
        unsigned int    esm_up_25g_txpreset_lane9  : 4  ; /* [15:12] */
        unsigned int    esm_dp_25g_txpreset_lane9  : 4  ; /* [11:8] */
        unsigned int    esm_up_25g_txpreset_lane8  : 4  ; /* [7:4] */
        unsigned int    esm_dp_25g_txpreset_lane8  : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CCIX_TS_CAP_REG30;

/* Define the union U_CCIX_TS_CAP_REG34 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    esm_up_25g_txpreset_lane15 : 4  ; /* [31:28] */
        unsigned int    esm_dp_25g_txpreset_lane15 : 4  ; /* [27:24] */
        unsigned int    esm_up_25g_txpreset_lane14 : 4  ; /* [23:20] */
        unsigned int    esm_dp_25g_txpreset_lane14 : 4  ; /* [19:16] */
        unsigned int    esm_up_25g_txpreset_lane13 : 4  ; /* [15:12] */
        unsigned int    esm_dp_25g_txpreset_lane13 : 4  ; /* [11:8] */
        unsigned int    esm_up_25g_txpreset_lane12 : 4  ; /* [7:4] */
        unsigned int    esm_dp_25g_txpreset_lane12 : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CCIX_TS_CAP_REG34;

/* Define the union U_CCIX_TS_CAP_REG38 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_143            : 31  ; /* [31:1] */
        unsigned int    opt_tlp_format_sup : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CCIX_TS_CAP_REG38;

/* Define the union U_CCIX_TS_CAP_REG3C */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_144           : 31  ; /* [31:1] */
        unsigned int    opt_tlp_format_en : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CCIX_TS_CAP_REG3C;

/* Define the union U_GEN4_PHY_CAP_REG00 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    gen4_phy_cap_next_cap_addr : 12  ; /* [31:20] */
        unsigned int    gen4_phy_cap_version       : 4  ; /* [19:16] */
        unsigned int    gen4_phy_capid             : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_GEN4_PHY_CAP_REG00;

/* Define the union U_GEN4_PHY_CAP_REG04 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_145 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_GEN4_PHY_CAP_REG04;

/* Define the union U_GEN4_PHY_CAP_REG08 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_146 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_GEN4_PHY_CAP_REG08;

/* Define the union U_GEN4_PHY_CAP_REG0C */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_147                    : 27  ; /* [31:5] */
        unsigned int    gen4_link_equalization_req : 1  ; /* [4] */
        unsigned int    gen4_eq_phase3_succ        : 1  ; /* [3] */
        unsigned int    gen4_eq_phase2_succ        : 1  ; /* [2] */
        unsigned int    gen4_eq_phase1_succ        : 1  ; /* [1] */
        unsigned int    gen4_eq_complete           : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_GEN4_PHY_CAP_REG0C;

/* Define the union U_GEN4_PHY_CAP_REG10 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_148               : 16  ; /* [31:16] */
        unsigned int    local_data_parity_err : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_GEN4_PHY_CAP_REG10;

/* Define the union U_GEN4_PHY_CAP_REG14 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_149                 : 16  ; /* [31:16] */
        unsigned int    retimer_data_parity_err : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_GEN4_PHY_CAP_REG14;

/* Define the union U_GEN4_PHY_CAP_REG18 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_150                  : 16  ; /* [31:16] */
        unsigned int    retimer2_data_parity_err : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_GEN4_PHY_CAP_REG18;

/* Define the union U_GEN4_PHY_CAP_REG1C */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_151 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_GEN4_PHY_CAP_REG1C;

/* Define the union U_GEN4_PHY_CAP_REG20 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    gen4_lane3_up_tx_preset : 4  ; /* [31:28] */
        unsigned int    gen4_lane3_dp_tx_preset : 4  ; /* [27:24] */
        unsigned int    gen4_lane2_up_tx_preset : 4  ; /* [23:20] */
        unsigned int    gen4_lane2_dp_tx_preset : 4  ; /* [19:16] */
        unsigned int    gen4_lane1_up_tx_preset : 4  ; /* [15:12] */
        unsigned int    gen4_lane1_dp_tx_preset : 4  ; /* [11:8] */
        unsigned int    gen4_lane0_up_tx_preset : 4  ; /* [7:4] */
        unsigned int    gen4_lane0_dp_tx_preset : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_GEN4_PHY_CAP_REG20;

/* Define the union U_GEN4_PHY_CAP_REG24 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    gen4_lane7_up_tx_preset : 4  ; /* [31:28] */
        unsigned int    gen4_lane7_dp_tx_preset : 4  ; /* [27:24] */
        unsigned int    gen4_lane6_up_tx_preset : 4  ; /* [23:20] */
        unsigned int    gen4_lane6_dp_tx_preset : 4  ; /* [19:16] */
        unsigned int    gen4_lane5_up_tx_preset : 4  ; /* [15:12] */
        unsigned int    gen4_lane5_dp_tx_preset : 4  ; /* [11:8] */
        unsigned int    gen4_lane4_up_tx_preset : 4  ; /* [7:4] */
        unsigned int    gen4_lane4_dp_tx_preset : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_GEN4_PHY_CAP_REG24;

/* Define the union U_GEN4_PHY_CAP_REG28 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    gen4_lane11_up_tx_preset : 4  ; /* [31:28] */
        unsigned int    gen4_lane11_dp_tx_preset : 4  ; /* [27:24] */
        unsigned int    gen4_lane10_up_tx_preset : 4  ; /* [23:20] */
        unsigned int    gen4_lane10_dp_tx_preset : 4  ; /* [19:16] */
        unsigned int    gen4_lane9_up_tx_preset  : 4  ; /* [15:12] */
        unsigned int    gen4_lane9_dp_tx_preset  : 4  ; /* [11:8] */
        unsigned int    gen4_lane8_up_tx_preset  : 4  ; /* [7:4] */
        unsigned int    gen4_lane8_dp_tx_preset  : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_GEN4_PHY_CAP_REG28;

/* Define the union U_GEN4_PHY_CAP_REG2C */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    gen4_lane15_up_tx_preset : 4  ; /* [31:28] */
        unsigned int    gen4_lane15_dp_tx_preset : 4  ; /* [27:24] */
        unsigned int    gen4_lane14_up_tx_preset : 4  ; /* [23:20] */
        unsigned int    gen4_lane14_dp_tx_preset : 4  ; /* [19:16] */
        unsigned int    gen4_lane13_up_tx_preset : 4  ; /* [15:12] */
        unsigned int    gen4_lane13_dp_tx_preset : 4  ; /* [11:8] */
        unsigned int    gen4_lane12_up_tx_preset : 4  ; /* [7:4] */
        unsigned int    gen4_lane12_dp_tx_preset : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_GEN4_PHY_CAP_REG2C;


//==============================================================================
/* Define the global struct */
typedef struct
{
    volatile U_PCIHDR_ID                       PCIHDR_ID                       ; /* 0 */
    volatile U_PCIHDR_CMDSTS                   PCIHDR_CMDSTS                   ; /* 4 */
    volatile U_PCIHDR_CLSREV                   PCIHDR_CLSREV                   ; /* 8 */
    volatile U_PCIHDR_MISC                     PCIHDR_MISC                     ; /* C */
    volatile U_PCIHDR_BAR0                     PCIHDR_BAR0                     ; /* 10 */
    volatile U_PCIHDR_BAR1                     PCIHDR_BAR1                     ; /* 14 */
    volatile U_PCIHDR_BUS_NUM                  PCIHDR_BUS_NUM                  ; /* 18 */
    volatile U_PCIHDR_IO_LIMIT                 PCIHDR_IO_LIMIT                 ; /* 1C */
    volatile U_PCIHDR_MEM_BASE_LIMIT           PCIHDR_MEM_BASE_LIMIT           ; /* 20 */
    volatile U_PCIHDR_PRE_MEM_BASE_LIMIT       PCIHDR_PRE_MEM_BASE_LIMIT       ; /* 24 */
    volatile U_PCIHDR_PRE_MEM_BASE_32_UPADR    PCIHDR_PRE_MEM_BASE_32_UPADR    ; /* 28 */
    volatile U_PCIHDR_PRE_MEM_LIMIT_32_UPADR   PCIHDR_PRE_MEM_LIMIT_32_UPADR   ; /* 2C */
    volatile U_PCIHDR_IO_UPADR                 PCIHDR_IO_UPADR                 ; /* 30 */
    volatile U_PCIHDR_CAPPTR                   PCIHDR_CAPPTR                   ; /* 34 */
    volatile U_PCIHDR_EXP_ROM_BASE             PCIHDR_EXP_ROM_BASE             ; /* 38 */
    volatile U_PCIHDR_INT                      PCIHDR_INT                      ; /* 3C */
    volatile U_PCIE_CAP_HEADER                 PCIE_CAP_HEADER                 ; /* 40 */
    volatile U_DEVICE_CAPBILITY                DEVICE_CAPBILITY                ; /* 44 */
    volatile U_DEVICE_CTRL_STATUS              DEVICE_CTRL_STATUS              ; /* 48 */
    volatile U_LINK_CAPBILITY                  LINK_CAPBILITY                  ; /* 4C */
    volatile U_LINK_CTRL_STATUS                LINK_CTRL_STATUS                ; /* 50 */
    volatile U_SLOT_CAPABILITY                 SLOT_CAPABILITY                 ; /* 54 */
    volatile U_SLOT_CTRL_STATUS                SLOT_CTRL_STATUS                ; /* 58 */
    volatile U_ROOT_CTRL_STATUS                ROOT_CTRL_STATUS                ; /* 5C */
    volatile U_ROOT_STATUS                     ROOT_STATUS                     ; /* 60 */
    volatile U_DEVICE_CAPABILITY2              DEVICE_CAPABILITY2              ; /* 64 */
    volatile U_DEVICE_CTRL2                    DEVICE_CTRL2                    ; /* 68 */
    volatile U_LINK_CAPABILITY2                LINK_CAPABILITY2                ; /* 6C */
    volatile U_LINK_CTRL_STATUS2               LINK_CTRL_STATUS2               ; /* 70 */
    volatile U_SLOT_CAP_2                      SLOT_CAP_2                      ; /* 74 */
    volatile U_SLOT_CTRL_2                     SLOT_CTRL_2                     ; /* 78 */
    volatile U_MSI_CAP_HEADER                  MSI_CAP_HEADER                  ; /* 80 */
    volatile U_MSI_LADDR                       MSI_LADDR                       ; /* 84 */
    volatile U_MSI_HADDR                       MSI_HADDR                       ; /* 88 */
    volatile U_MSI_DATA                        MSI_DATA                        ; /* 8C */
    volatile U_MSI_MASK                        MSI_MASK                        ; /* 90 */
    volatile U_MSI_PENDING                     MSI_PENDING                     ; /* 94 */
    volatile U_PME_CAP_HEADER                  PME_CAP_HEADER                  ; /* B0 */
    volatile U_PME_STATUS                      PME_STATUS                      ; /* B4 */
    volatile U_SID_CAP_HEADER                  SID_CAP_HEADER                  ; /* D0 */
    volatile U_SSVID_SSID                      SSVID_SSID                      ; /* D4 */
    volatile U_AER_CAP_HEADER                  AER_CAP_HEADER                  ; /* 100 */
    volatile U_UNCR_ERR_STATUS                 UNCR_ERR_STATUS                 ; /* 104 */
    volatile U_UNCR_ERR_MASK                   UNCR_ERR_MASK                   ; /* 108 */
    volatile U_UNCR_ERR_SEVERITY               UNCR_ERR_SEVERITY               ; /* 10C */
    volatile U_COR_ERR_STATUS                  COR_ERR_STATUS                  ; /* 110 */
    volatile U_COR_ERR_MASK                    COR_ERR_MASK                    ; /* 114 */
    volatile U_ADVACD_CAP_CTRL                 ADVACD_CAP_CTRL                 ; /* 118 */
    volatile U_FIRST_HEADER_LOG                FIRST_HEADER_LOG                ; /* 11C */
    volatile U_SECOND_HEADER_LOG               SECOND_HEADER_LOG               ; /* 120 */
    volatile U_THIRD_HEADER_LOG                THIRD_HEADER_LOG                ; /* 124 */
    volatile U_FOUR_HEADER_LOG                 FOUR_HEADER_LOG                 ; /* 128 */
    volatile U_ROOT_ERROR_COMMAND              ROOT_ERROR_COMMAND              ; /* 12C */
    volatile U_ROOT_ERROR_STATUS               ROOT_ERROR_STATUS               ; /* 130 */
    volatile U_ERR_SOURCE_IDEN                 ERR_SOURCE_IDEN                 ; /* 134 */
    volatile U_FIRST_PREFIX_LOG                FIRST_PREFIX_LOG                ; /* 138 */
    volatile U_SECOND_PREFIX_LOG               SECOND_PREFIX_LOG               ; /* 13C */
    volatile U_THIRD_PREFIX_LOG                THIRD_PREFIX_LOG                ; /* 140 */
    volatile U_FOUR_PREFIX_LOG                 FOUR_PREFIX_LOG                 ; /* 144 */
    volatile U_TPH_EXTEND_CAP                  TPH_EXTEND_CAP                  ; /* 2A0 */
    volatile U_TPH_REQ_CAP                     TPH_REQ_CAP                     ; /* 2A4 */
    volatile U_TPH_REQ_CTRL                    TPH_REQ_CTRL                    ; /* 2A8 */
    volatile U_SECONDARY_PCIE_EXT_CAP_HED      SECONDARY_PCIE_EXT_CAP_HED      ; /* 310 */
    volatile U_LINK_CONTROL3_REGISTER          LINK_CONTROL3_REGISTER          ; /* 314 */
    volatile U_LANE_ERROR_STATUS_REG           LANE_ERROR_STATUS_REG           ; /* 318 */
    volatile U_LINK_CONTROL3_REGISTER01        LINK_CONTROL3_REGISTER01        ; /* 31C */
    volatile U_LINK_CONTROL3_REGISTER23        LINK_CONTROL3_REGISTER23        ; /* 320 */
    volatile U_LINK_CONTROL3_REGISTER45        LINK_CONTROL3_REGISTER45        ; /* 324 */
    volatile U_LINK_CONTROL3_REGISTER67        LINK_CONTROL3_REGISTER67        ; /* 328 */
    volatile U_LINK_CONTROL3_REGISTER89        LINK_CONTROL3_REGISTER89        ; /* 32C */
    volatile U_LINK_CONTROL3_REGISTER1011      LINK_CONTROL3_REGISTER1011      ; /* 330 */
    volatile U_LINK_CONTROL3_REGISTER1213      LINK_CONTROL3_REGISTER1213      ; /* 334 */
    volatile U_LINK_CONTROL3_REGISTER1415      LINK_CONTROL3_REGISTER1415      ; /* 338 */
    volatile U_VC_CAP_0X00                     VC_CAP_0X00                     ; /* 400 */
    volatile U_VC_CAP_0X04                     VC_CAP_0X04                     ; /* 404 */
    volatile U_VC_CAP_0X08                     VC_CAP_0X08                     ; /* 408 */
    volatile U_VC_CAP_0X0C                     VC_CAP_0X0C                     ; /* 40C */
    volatile U_VC_CAP_0X10                     VC_CAP_0X10                     ; /* 410 */
    volatile U_VC_CAP_0X14                     VC_CAP_0X14                     ; /* 414 */
    volatile U_VC_CAP_0X18                     VC_CAP_0X18                     ; /* 418 */
    volatile U_VC_CAP_0X1C                     VC_CAP_0X1C                     ; /* 41C */
    volatile U_VC_CAP_0X20                     VC_CAP_0X20                     ; /* 420 */
    volatile U_VC_CAP_0X24                     VC_CAP_0X24                     ; /* 424 */
    volatile U_DEVICE_SERIAL_NUMBER_CAP_HEADER DEVICE_SERIAL_NUMBER_CAP_HEADER ; /* 4E0 */
    volatile U_SERIAL_LNUM                     SERIAL_LNUM                     ; /* 4E4 */
    volatile U_SERIAL_HNUM                     SERIAL_HNUM                     ; /* 4E8 */
    volatile U_ACS_CAP_0X00                    ACS_CAP_0X00                    ; /* 630 */
    volatile U_ACS_CAP_0X04                    ACS_CAP_0X04                    ; /* 634 */
    volatile U_DPC_CAP_0X00                    DPC_CAP_0X00                    ; /* 680 */
    volatile U_DPC_CAP_0X04                    DPC_CAP_0X04                    ; /* 684 */
    volatile U_DPC_CAP_0X08                    DPC_CAP_0X08                    ; /* 688 */
    volatile U_DPC_CAP_0X0C                    DPC_CAP_0X0C                    ; /* 68C */
    volatile U_DPC_CAP_0X10                    DPC_CAP_0X10                    ; /* 690 */
    volatile U_DPC_CAP_0X14                    DPC_CAP_0X14                    ; /* 694 */
    volatile U_DPC_CAP_0X18                    DPC_CAP_0X18                    ; /* 698 */
    volatile U_DPC_CAP_0X1C                    DPC_CAP_0X1C                    ; /* 69C */
    volatile U_DPC_CAP_0X20                    DPC_CAP_0X20                    ; /* 6A0 */
    volatile U_DPC_CAP_0X24                    DPC_CAP_0X24                    ; /* 6A4 */
    volatile U_DPC_CAP_0X28                    DPC_CAP_0X28                    ; /* 6A8 */
    volatile U_DPC_CAP_0X2C                    DPC_CAP_0X2C                    ; /* 6AC */
    volatile U_DPC_CAP_0X30                    DPC_CAP_0X30                    ; /* 6B0 */
    volatile U_DPC_CAP_0X34                    DPC_CAP_0X34                    ; /* 6B4 */
    volatile U_DPC_CAP_0X38                    DPC_CAP_0X38                    ; /* 6B8 */
    volatile U_DPC_CAP_0X3C                    DPC_CAP_0X3C                    ; /* 6BC */
    volatile U_DPC_CAP_0X40                    DPC_CAP_0X40                    ; /* 6C0 */
    volatile U_DL_FEATURE_CAP_REG00            DL_FEATURE_CAP_REG00            ; /* 700 */
    volatile U_DL_FEATURE_CAP_REG04            DL_FEATURE_CAP_REG04            ; /* 704 */
    volatile U_DL_FEATURE_CAP_REG08            DL_FEATURE_CAP_REG08            ; /* 708 */
    volatile U_RXMARGIN_CAP_REG00              RXMARGIN_CAP_REG00              ; /* 70C */
    volatile U_RXMARGIN_CAP_REG04              RXMARGIN_CAP_REG04              ; /* 710 */
    volatile U_RXMARGIN_CAP_REG08              RXMARGIN_CAP_REG08[16]          ; /* 714 */
    volatile U_CCIX_TS_CAP_REG00               CCIX_TS_CAP_REG00               ; /* 800 */
    volatile U_CCIX_TS_CAP_REG04               CCIX_TS_CAP_REG04               ; /* 804 */
    volatile U_CCIX_TS_CAP_REG08               CCIX_TS_CAP_REG08               ; /* 808 */
    volatile U_CCIX_TS_CAP_REG0C               CCIX_TS_CAP_REG0C               ; /* 80C */
    volatile U_CCIX_TS_CAP_REG10               CCIX_TS_CAP_REG10               ; /* 810 */
    volatile U_CCIX_TS_CAP_REG14               CCIX_TS_CAP_REG14               ; /* 814 */
    volatile U_CCIX_TS_CAP_REG18               CCIX_TS_CAP_REG18               ; /* 818 */
    volatile U_CCIX_TS_CAP_REG1C               CCIX_TS_CAP_REG1C               ; /* 81C */
    volatile U_CCIX_TS_CAP_REG20               CCIX_TS_CAP_REG20               ; /* 820 */
    volatile U_CCIX_TS_CAP_REG24               CCIX_TS_CAP_REG24               ; /* 824 */
    volatile U_CCIX_TS_CAP_REG28               CCIX_TS_CAP_REG28               ; /* 828 */
    volatile U_CCIX_TS_CAP_REG2C               CCIX_TS_CAP_REG2C               ; /* 82C */
    volatile U_CCIX_TS_CAP_REG30               CCIX_TS_CAP_REG30               ; /* 830 */
    volatile U_CCIX_TS_CAP_REG34               CCIX_TS_CAP_REG34               ; /* 834 */
    volatile U_CCIX_TS_CAP_REG38               CCIX_TS_CAP_REG38               ; /* 838 */
    volatile U_CCIX_TS_CAP_REG3C               CCIX_TS_CAP_REG3C               ; /* 83C */
    volatile U_GEN4_PHY_CAP_REG00              GEN4_PHY_CAP_REG00              ; /* 880 */
    volatile U_GEN4_PHY_CAP_REG04              GEN4_PHY_CAP_REG04              ; /* 884 */
    volatile U_GEN4_PHY_CAP_REG08              GEN4_PHY_CAP_REG08              ; /* 888 */
    volatile U_GEN4_PHY_CAP_REG0C              GEN4_PHY_CAP_REG0C              ; /* 88C */
    volatile U_GEN4_PHY_CAP_REG10              GEN4_PHY_CAP_REG10              ; /* 890 */
    volatile U_GEN4_PHY_CAP_REG14              GEN4_PHY_CAP_REG14              ; /* 894 */
    volatile U_GEN4_PHY_CAP_REG18              GEN4_PHY_CAP_REG18              ; /* 898 */
    volatile U_GEN4_PHY_CAP_REG1C              GEN4_PHY_CAP_REG1C              ; /* 89C */
    volatile U_GEN4_PHY_CAP_REG20              GEN4_PHY_CAP_REG20              ; /* 8A0 */
    volatile U_GEN4_PHY_CAP_REG24              GEN4_PHY_CAP_REG24              ; /* 8A4 */
    volatile U_GEN4_PHY_CAP_REG28              GEN4_PHY_CAP_REG28              ; /* 8A8 */
    volatile U_GEN4_PHY_CAP_REG2C              GEN4_PHY_CAP_REG2C              ; /* 8AC */

} S_hipciec_rp_cfgspace_2_REGS_TYPE;

/* Declare the struct pointor of the module hipciec_rp_cfgspace_2 */
extern volatile S_hipciec_rp_cfgspace_2_REGS_TYPE *gophipciec_rp_cfgspace_2AllReg;

/* Declare the functions that set the member value */
int iSetPCIHDR_ID_device_id(unsigned int udevice_id);
int iSetPCIHDR_ID_vendor_id(unsigned int uvendor_id);
int iSetPCIHDR_CMDSTS_cfg_detected_par_err(unsigned int ucfg_detected_par_err);
int iSetPCIHDR_CMDSTS_cfg_rx_sys_err(unsigned int ucfg_rx_sys_err);
int iSetPCIHDR_CMDSTS_cfg_rx_master_abort(unsigned int ucfg_rx_master_abort);
int iSetPCIHDR_CMDSTS_cfg_rx_target_abort(unsigned int ucfg_rx_target_abort);
int iSetPCIHDR_CMDSTS_cfg_sig_target_abort(unsigned int ucfg_sig_target_abort);
int iSetPCIHDR_CMDSTS_cfg_devsel_timing(unsigned int ucfg_devsel_timing);
int iSetPCIHDR_CMDSTS_cfg_mdata_par_err(unsigned int ucfg_mdata_par_err);
int iSetPCIHDR_CMDSTS_cfg_fastb2b_cap(unsigned int ucfg_fastb2b_cap);
int iSetPCIHDR_CMDSTS_cfg_66mhz_cap(unsigned int ucfg_66mhz_cap);
int iSetPCIHDR_CMDSTS_cfg_cap_list(unsigned int ucfg_cap_list);
int iSetPCIHDR_CMDSTS_cfg_intx_status(unsigned int ucfg_intx_status);
int iSetPCIHDR_CMDSTS_immediate_readiness(unsigned int uimmediate_readiness);
int iSetPCIHDR_CMDSTS_cfg_intx_disable(unsigned int ucfg_intx_disable);
int iSetPCIHDR_CMDSTS_cfg_fast_b2b_en(unsigned int ucfg_fast_b2b_en);
int iSetPCIHDR_CMDSTS_cfg_serr_en(unsigned int ucfg_serr_en);
int iSetPCIHDR_CMDSTS_idsel_stepp_wait_cly_ctr(unsigned int uidsel_stepp_wait_cly_ctr);
int iSetPCIHDR_CMDSTS_cfg_parity_err_resp(unsigned int ucfg_parity_err_resp);
int iSetPCIHDR_CMDSTS_cfg_vga_snoop_en(unsigned int ucfg_vga_snoop_en);
int iSetPCIHDR_CMDSTS_cfg_mem_wr_invld_en(unsigned int ucfg_mem_wr_invld_en);
int iSetPCIHDR_CMDSTS_cfg_special_cycle_en(unsigned int ucfg_special_cycle_en);
int iSetPCIHDR_CMDSTS_cfg_master_en(unsigned int ucfg_master_en);
int iSetPCIHDR_CMDSTS_cfg_mem_space_en(unsigned int ucfg_mem_space_en);
int iSetPCIHDR_CMDSTS_cfg_io_space_en(unsigned int ucfg_io_space_en);
int iSetPCIHDR_CLSREV_base_class_code(unsigned int ubase_class_code);
int iSetPCIHDR_CLSREV_sub_class_code(unsigned int usub_class_code);
int iSetPCIHDR_CLSREV_program_inf(unsigned int uprogram_inf);
int iSetPCIHDR_CLSREV_revision_id(unsigned int urevision_id);
int iSetPCIHDR_MISC_bist_cap(unsigned int ubist_cap);
int iSetPCIHDR_MISC_start_bist(unsigned int ustart_bist);
int iSetPCIHDR_MISC_bist_result(unsigned int ubist_result);
int iSetPCIHDR_MISC_multi_func_deivce(unsigned int umulti_func_deivce);
int iSetPCIHDR_MISC_cfg_header_type(unsigned int ucfg_header_type);
int iSetPCIHDR_MISC_cfg_latency_timer(unsigned int ucfg_latency_timer);
int iSetPCIHDR_MISC_cfg_cachlie_size(unsigned int ucfg_cachlie_size);
int iSetPCIHDR_BAR0_cfg_bar0_addr(unsigned int ucfg_bar0_addr);
int iSetPCIHDR_BAR0_cfg_bar0_prefetch_en(unsigned int ucfg_bar0_prefetch_en);
int iSetPCIHDR_BAR0_cfg_bar0_width(unsigned int ucfg_bar0_width);
int iSetPCIHDR_BAR0_cfg_bar0_type(unsigned int ucfg_bar0_type);
int iSetPCIHDR_BAR1_cfg_bar1_addr(unsigned int ucfg_bar1_addr);
int iSetPCIHDR_BAR1_cfg_bar1_prefetch_en(unsigned int ucfg_bar1_prefetch_en);
int iSetPCIHDR_BAR1_cfg_bar1_width(unsigned int ucfg_bar1_width);
int iSetPCIHDR_BAR1_cfg_bar1_type(unsigned int ucfg_bar1_type);
int iSetPCIHDR_BUS_NUM_sec_lat_timer(unsigned int usec_lat_timer);
int iSetPCIHDR_BUS_NUM_sub_bus_num(unsigned int usub_bus_num);
int iSetPCIHDR_BUS_NUM_sec_bus_num(unsigned int usec_bus_num);
int iSetPCIHDR_BUS_NUM_pri_bus_num(unsigned int upri_bus_num);
int iSetPCIHDR_IO_LIMIT_sec_detect_parity_err(unsigned int usec_detect_parity_err);
int iSetPCIHDR_IO_LIMIT_sec_received_system_err(unsigned int usec_received_system_err);
int iSetPCIHDR_IO_LIMIT_sec_received_master_abort(unsigned int usec_received_master_abort);
int iSetPCIHDR_IO_LIMIT_sec_received_target_abort(unsigned int usec_received_target_abort);
int iSetPCIHDR_IO_LIMIT_sec_signal_target_abort(unsigned int usec_signal_target_abort);
int iSetPCIHDR_IO_LIMIT_sec_devsel_timing(unsigned int usec_devsel_timing);
int iSetPCIHDR_IO_LIMIT_sec_master_date_parity_err(unsigned int usec_master_date_parity_err);
int iSetPCIHDR_IO_LIMIT_sec_fast_b2b_cap(unsigned int usec_fast_b2b_cap);
int iSetPCIHDR_IO_LIMIT_sec_66mhz_cap(unsigned int usec_66mhz_cap);
int iSetPCIHDR_IO_LIMIT_cfg_io_low_limit(unsigned int ucfg_io_low_limit);
int iSetPCIHDR_IO_LIMIT_cfg_io_low_limit_sup(unsigned int ucfg_io_low_limit_sup);
int iSetPCIHDR_IO_LIMIT_cfg_io_low_base(unsigned int ucfg_io_low_base);
int iSetPCIHDR_IO_LIMIT_cfg_io_low_base_sup(unsigned int ucfg_io_low_base_sup);
int iSetPCIHDR_MEM_BASE_LIMIT_mem_limit(unsigned int umem_limit);
int iSetPCIHDR_MEM_BASE_LIMIT_mem_base(unsigned int umem_base);
int iSetPCIHDR_PRE_MEM_BASE_LIMIT_prefetch_mem_limit_h(unsigned int uprefetch_mem_limit_h);
int iSetPCIHDR_PRE_MEM_BASE_LIMIT_prefetch_mem_limit_l(unsigned int uprefetch_mem_limit_l);
int iSetPCIHDR_PRE_MEM_BASE_LIMIT_prefetch_mem_base_h(unsigned int uprefetch_mem_base_h);
int iSetPCIHDR_PRE_MEM_BASE_LIMIT_prefetch_mem_base_l(unsigned int uprefetch_mem_base_l);
int iSetPCIHDR_PRE_MEM_BASE_32_UPADR_prefetch_mem_base_up32bit(unsigned int uprefetch_mem_base_up32bit);
int iSetPCIHDR_PRE_MEM_LIMIT_32_UPADR_prefetch_mem_limit_up32bit(unsigned int uprefetch_mem_limit_up32bit);
int iSetPCIHDR_IO_UPADR_io_limit_up16bit(unsigned int uio_limit_up16bit);
int iSetPCIHDR_IO_UPADR_io_base_up16bit(unsigned int uio_base_up16bit);
int iSetPCIHDR_CAPPTR_cfg_cap_ptr(unsigned int ucfg_cap_ptr);
int iSetPCIHDR_EXP_ROM_BASE_ext_rom_base_address(unsigned int uext_rom_base_address);
int iSetPCIHDR_EXP_ROM_BASE_ext_rom_enable(unsigned int uext_rom_enable);
int iSetPCIHDR_INT_bridge_timer_serr_en(unsigned int ubridge_timer_serr_en);
int iSetPCIHDR_INT_bridge_discard_timer_status(unsigned int ubridge_discard_timer_status);
int iSetPCIHDR_INT_bridge_sec_discard_timer(unsigned int ubridge_sec_discard_timer);
int iSetPCIHDR_INT_bridge_pri_discard_timer(unsigned int ubridge_pri_discard_timer);
int iSetPCIHDR_INT_bridge_fast_b2b_en(unsigned int ubridge_fast_b2b_en);
int iSetPCIHDR_INT_bridge_sec_bus_reset(unsigned int ubridge_sec_bus_reset);
int iSetPCIHDR_INT_bridge_master_abort_mode(unsigned int ubridge_master_abort_mode);
int iSetPCIHDR_INT_bridge_vga16bit_decode(unsigned int ubridge_vga16bit_decode);
int iSetPCIHDR_INT_bridge_vga_en(unsigned int ubridge_vga_en);
int iSetPCIHDR_INT_bridge_isa_en(unsigned int ubridge_isa_en);
int iSetPCIHDR_INT_bridge_serr_en(unsigned int ubridge_serr_en);
int iSetPCIHDR_INT_bridge_parity_err_resp_en(unsigned int ubridge_parity_err_resp_en);
int iSetPCIHDR_INT_cfg_int_pin(unsigned int ucfg_int_pin);
int iSetPCIHDR_INT_cfg_int_line(unsigned int ucfg_int_line);
int iSetPCIE_CAP_HEADER_undefine_00(unsigned int uundefine_00);
int iSetPCIE_CAP_HEADER_int_msg_num(unsigned int uint_msg_num);
int iSetPCIE_CAP_HEADER_slot_implement(unsigned int uslot_implement);
int iSetPCIE_CAP_HEADER_port_type(unsigned int uport_type);
int iSetPCIE_CAP_HEADER_pci_cap_ver(unsigned int upci_cap_ver);
int iSetPCIE_CAP_HEADER_pcie_next_cap_addr(unsigned int upcie_next_cap_addr);
int iSetPCIE_CAP_HEADER_pci_capid(unsigned int upci_capid);
int iSetDEVICE_CAPBILITY_flr_cap(unsigned int uflr_cap);
int iSetDEVICE_CAPBILITY_cap_slot_pwr_sca(unsigned int ucap_slot_pwr_sca);
int iSetDEVICE_CAPBILITY_cap_slot_pwr_limit_val(unsigned int ucap_slot_pwr_limit_val);
int iSetDEVICE_CAPBILITY_ro_base_err_rpt(unsigned int uro_base_err_rpt);
int iSetDEVICE_CAPBILITY_undefine_04(unsigned int uundefine_04);
int iSetDEVICE_CAPBILITY_ep_l1_accept_lat(unsigned int uep_l1_accept_lat);
int iSetDEVICE_CAPBILITY_ep_l0s_accept_lat(unsigned int uep_l0s_accept_lat);
int iSetDEVICE_CAPBILITY_ext_tag_sup(unsigned int uext_tag_sup);
int iSetDEVICE_CAPBILITY_phantom_fun_sup(unsigned int uphantom_fun_sup);
int iSetDEVICE_CAPBILITY_max_payload_size_support(unsigned int umax_payload_size_support);
int iSetDEVICE_CTRL_STATUS_emergency_pwr_reduce_det(unsigned int uemergency_pwr_reduce_det);
int iSetDEVICE_CTRL_STATUS_tlp_pending(unsigned int utlp_pending);
int iSetDEVICE_CTRL_STATUS_aux_pwr_detect(unsigned int uaux_pwr_detect);
int iSetDEVICE_CTRL_STATUS_ur_detect(unsigned int uur_detect);
int iSetDEVICE_CTRL_STATUS_fat_err_detect(unsigned int ufat_err_detect);
int iSetDEVICE_CTRL_STATUS_non_fata_detect(unsigned int unon_fata_detect);
int iSetDEVICE_CTRL_STATUS_cor_err_detect(unsigned int ucor_err_detect);
int iSetDEVICE_CTRL_STATUS_max_read_req_size(unsigned int umax_read_req_size);
int iSetDEVICE_CTRL_STATUS_no_snoop_en(unsigned int uno_snoop_en);
int iSetDEVICE_CTRL_STATUS_aux_pwr_pm_en(unsigned int uaux_pwr_pm_en);
int iSetDEVICE_CTRL_STATUS_phantom_func_en(unsigned int uphantom_func_en);
int iSetDEVICE_CTRL_STATUS_extend_tag_en(unsigned int uextend_tag_en);
int iSetDEVICE_CTRL_STATUS_max_payload_size(unsigned int umax_payload_size);
int iSetDEVICE_CTRL_STATUS_relax_order_en(unsigned int urelax_order_en);
int iSetDEVICE_CTRL_STATUS_ur_rpt_en(unsigned int uur_rpt_en);
int iSetDEVICE_CTRL_STATUS_fat_err_rpt_en(unsigned int ufat_err_rpt_en);
int iSetDEVICE_CTRL_STATUS_non_fat_rpt_en(unsigned int unon_fat_rpt_en);
int iSetDEVICE_CTRL_STATUS_cor_err_rpt_en(unsigned int ucor_err_rpt_en);
int iSetLINK_CAPBILITY_port_num(unsigned int uport_num);
int iSetLINK_CAPBILITY_aspm_opt_compliance(unsigned int uaspm_opt_compliance);
int iSetLINK_CAPBILITY_link_band_notice_cap(unsigned int ulink_band_notice_cap);
int iSetLINK_CAPBILITY_dl_link_act_rpt_cap(unsigned int udl_link_act_rpt_cap);
int iSetLINK_CAPBILITY_surprise_dn_err_rpt_cap(unsigned int usurprise_dn_err_rpt_cap);
int iSetLINK_CAPBILITY_clock_pm(unsigned int uclock_pm);
int iSetLINK_CAPBILITY_l1_exit_lat(unsigned int ul1_exit_lat);
int iSetLINK_CAPBILITY_l0_exit_lat(unsigned int ul0_exit_lat);
int iSetLINK_CAPBILITY_aspm_sup(unsigned int uaspm_sup);
int iSetLINK_CAPBILITY_max_link_width(unsigned int umax_link_width);
int iSetLINK_CAPBILITY_max_link_speed(unsigned int umax_link_speed);
int iSetLINK_CTRL_STATUS_link_auto_band_status(unsigned int ulink_auto_band_status);
int iSetLINK_CTRL_STATUS_link_band_status(unsigned int ulink_band_status);
int iSetLINK_CTRL_STATUS_dl_cfg_link_active(unsigned int udl_cfg_link_active);
int iSetLINK_CTRL_STATUS_slot_clk_cfg(unsigned int uslot_clk_cfg);
int iSetLINK_CTRL_STATUS_link_training(unsigned int ulink_training);
int iSetLINK_CTRL_STATUS_undefined_12(unsigned int uundefined_12);
int iSetLINK_CTRL_STATUS_mac_cur_link_width(unsigned int umac_cur_link_width);
int iSetLINK_CTRL_STATUS_mac_cur_link_speed(unsigned int umac_cur_link_speed);
int iSetLINK_CTRL_STATUS_drs_signal_ctrl(unsigned int udrs_signal_ctrl);
int iSetLINK_CTRL_STATUS_link_auto_band_int_en(unsigned int ulink_auto_band_int_en);
int iSetLINK_CTRL_STATUS_link_band_int_en(unsigned int ulink_band_int_en);
int iSetLINK_CTRL_STATUS_hw_auto_width_dis(unsigned int uhw_auto_width_dis);
int iSetLINK_CTRL_STATUS_clock_pm_en(unsigned int uclock_pm_en);
int iSetLINK_CTRL_STATUS_extended_sync(unsigned int uextended_sync);
int iSetLINK_CTRL_STATUS_common_clk_cfg(unsigned int ucommon_clk_cfg);
int iSetLINK_CTRL_STATUS_retrain_link(unsigned int uretrain_link);
int iSetLINK_CTRL_STATUS_link_disable(unsigned int ulink_disable);
int iSetLINK_CTRL_STATUS_rcb(unsigned int urcb);
int iSetLINK_CTRL_STATUS_aspm_ctrl(unsigned int uaspm_ctrl);
int iSetSLOT_CAPABILITY_physical_slot_num(unsigned int uphysical_slot_num);
int iSetSLOT_CAPABILITY_no_comman_cpled_sup(unsigned int uno_comman_cpled_sup);
int iSetSLOT_CAPABILITY_elec_interlock_pre(unsigned int uelec_interlock_pre);
int iSetSLOT_CAPABILITY_slot_pwr_limit_scale(unsigned int uslot_pwr_limit_scale);
int iSetSLOT_CAPABILITY_slot_pwr_limit_val(unsigned int uslot_pwr_limit_val);
int iSetSLOT_CAPABILITY_hot_plug_cap(unsigned int uhot_plug_cap);
int iSetSLOT_CAPABILITY_hot_plug_surprise(unsigned int uhot_plug_surprise);
int iSetSLOT_CAPABILITY_pwr_indicator_pre(unsigned int upwr_indicator_pre);
int iSetSLOT_CAPABILITY_att_indecator_pre(unsigned int uatt_indecator_pre);
int iSetSLOT_CAPABILITY_msl_sensor_pre(unsigned int umsl_sensor_pre);
int iSetSLOT_CAPABILITY_pwr_ctrl_pre(unsigned int upwr_ctrl_pre);
int iSetSLOT_CAPABILITY_att_button_pre(unsigned int uatt_button_pre);
int iSetSLOT_CTRL_STATUS_dl_state_change(unsigned int udl_state_change);
int iSetSLOT_CTRL_STATUS_elec_interlock_st(unsigned int uelec_interlock_st);
int iSetSLOT_CTRL_STATUS_presencd_det_st(unsigned int upresencd_det_st);
int iSetSLOT_CTRL_STATUS_mrl_sensor_st(unsigned int umrl_sensor_st);
int iSetSLOT_CTRL_STATUS_command_cpled(unsigned int ucommand_cpled);
int iSetSLOT_CTRL_STATUS_presencd_det_change(unsigned int upresencd_det_change);
int iSetSLOT_CTRL_STATUS_mrl_sensor_change(unsigned int umrl_sensor_change);
int iSetSLOT_CTRL_STATUS_pwr_fault_det(unsigned int upwr_fault_det);
int iSetSLOT_CTRL_STATUS_attention_button(unsigned int uattention_button);
int iSetSLOT_CTRL_STATUS_auto_slot_plmt_disable(unsigned int uauto_slot_plmt_disable);
int iSetSLOT_CTRL_STATUS_dl_state_change_en(unsigned int udl_state_change_en);
int iSetSLOT_CTRL_STATUS_elec_interlock_ctrl(unsigned int uelec_interlock_ctrl);
int iSetSLOT_CTRL_STATUS_pwr_ctrled_ctrl(unsigned int upwr_ctrled_ctrl);
int iSetSLOT_CTRL_STATUS_pwr_indicator_ctrl(unsigned int upwr_indicator_ctrl);
int iSetSLOT_CTRL_STATUS_att_indicator_ctrl(unsigned int uatt_indicator_ctrl);
int iSetSLOT_CTRL_STATUS_hot_plug_int_en(unsigned int uhot_plug_int_en);
int iSetSLOT_CTRL_STATUS_command_cpled_int_en(unsigned int ucommand_cpled_int_en);
int iSetSLOT_CTRL_STATUS_presence_det_change_en(unsigned int upresence_det_change_en);
int iSetSLOT_CTRL_STATUS_mrl_sensor_change_en(unsigned int umrl_sensor_change_en);
int iSetSLOT_CTRL_STATUS_pwr_fault_det_en(unsigned int upwr_fault_det_en);
int iSetSLOT_CTRL_STATUS_att_buttom_pre_en(unsigned int uatt_buttom_pre_en);
int iSetROOT_CTRL_STATUS_crs_sw_visibility(unsigned int ucrs_sw_visibility);
int iSetROOT_CTRL_STATUS_crs_sw_visibility_en(unsigned int ucrs_sw_visibility_en);
int iSetROOT_CTRL_STATUS_pme_int_en(unsigned int upme_int_en);
int iSetROOT_CTRL_STATUS_sys_err_on_fat_err_en(unsigned int usys_err_on_fat_err_en);
int iSetROOT_CTRL_STATUS_sys_err_on_non_fat_en(unsigned int usys_err_on_non_fat_en);
int iSetROOT_CTRL_STATUS_sys_err_on_cor_err_en(unsigned int usys_err_on_cor_err_en);
int iSetROOT_STATUS_pme_pending(unsigned int upme_pending);
int iSetROOT_STATUS_pme_status_rt(unsigned int upme_status_rt);
int iSetROOT_STATUS_pme_rid(unsigned int upme_rid);
int iSetDEVICE_CAPABILITY2_frs_sup(unsigned int ufrs_sup);
int iSetDEVICE_CAPABILITY2_emergency_pwr_reduce_init_req(unsigned int uemergency_pwr_reduce_init_req);
int iSetDEVICE_CAPABILITY2_emergency_pwr_reduce_sup(unsigned int uemergency_pwr_reduce_sup);
int iSetDEVICE_CAPABILITY2_max_end_end_pfx(unsigned int umax_end_end_pfx);
int iSetDEVICE_CAPABILITY2_end_end_pfx_sup(unsigned int uend_end_pfx_sup);
int iSetDEVICE_CAPABILITY2_ext_fmt_sup(unsigned int uext_fmt_sup);
int iSetDEVICE_CAPABILITY2_obff_sup(unsigned int uobff_sup);
int iSetDEVICE_CAPABILITY2_sup_10bit_req_tag(unsigned int usup_10bit_req_tag);
int iSetDEVICE_CAPABILITY2_sup_10bit_cpl_tag(unsigned int usup_10bit_cpl_tag);
int iSetDEVICE_CAPABILITY2_ln_sys_cls(unsigned int uln_sys_cls);
int iSetDEVICE_CAPABILITY2_tph_cpl_sup(unsigned int utph_cpl_sup);
int iSetDEVICE_CAPABILITY2_ltr_mech_sup(unsigned int ultr_mech_sup);
int iSetDEVICE_CAPABILITY2_no_roen_prpr_pass(unsigned int uno_roen_prpr_pass);
int iSetDEVICE_CAPABILITY2_cas_128bit_cpl_sup(unsigned int ucas_128bit_cpl_sup);
int iSetDEVICE_CAPABILITY2_atomic_64bit_cpl_sup(unsigned int uatomic_64bit_cpl_sup);
int iSetDEVICE_CAPABILITY2_atomic_32bit_cpl_sup(unsigned int uatomic_32bit_cpl_sup);
int iSetDEVICE_CAPABILITY2_atomicop_route_sup(unsigned int uatomicop_route_sup);
int iSetDEVICE_CAPABILITY2_ari_fwd_sup(unsigned int uari_fwd_sup);
int iSetDEVICE_CAPABILITY2_cpl_timeout_disable_sup(unsigned int ucpl_timeout_disable_sup);
int iSetDEVICE_CAPABILITY2_cpl_timeout_range(unsigned int ucpl_timeout_range);
int iSetDEVICE_CTRL2_end_end_pfx_blk(unsigned int uend_end_pfx_blk);
int iSetDEVICE_CTRL2_obff_en(unsigned int uobff_en);
int iSetDEVICE_CTRL2_en_10bit_req_tag(unsigned int uen_10bit_req_tag);
int iSetDEVICE_CTRL2_emergency_pwr_reduce_req(unsigned int uemergency_pwr_reduce_req);
int iSetDEVICE_CTRL2_ltr_mech_en(unsigned int ultr_mech_en);
int iSetDEVICE_CTRL2_ido_cpl_en(unsigned int uido_cpl_en);
int iSetDEVICE_CTRL2_ido_req_en(unsigned int uido_req_en);
int iSetDEVICE_CTRL2_atomicop_egress_blk(unsigned int uatomicop_egress_blk);
int iSetDEVICE_CTRL2_atomicop_req_en(unsigned int uatomicop_req_en);
int iSetDEVICE_CTRL2_ari_fwd_en(unsigned int uari_fwd_en);
int iSetDEVICE_CTRL2_cpl_timeout_dis(unsigned int ucpl_timeout_dis);
int iSetDEVICE_CTRL2_cpl_timeout_value(unsigned int ucpl_timeout_value);
int iSetLINK_CAPABILITY2_drs_sup(unsigned int udrs_sup);
int iSetLINK_CAPABILITY2_retimer2_presence_detect_sup(unsigned int uretimer2_presence_detect_sup);
int iSetLINK_CAPABILITY2_retimer_presence_detect_sup(unsigned int uretimer_presence_detect_sup);
int iSetLINK_CAPABILITY2_cfg_rx_lower_skp_cap(unsigned int ucfg_rx_lower_skp_cap);
int iSetLINK_CAPABILITY2_cfg_tx_lower_skp_cap(unsigned int ucfg_tx_lower_skp_cap);
int iSetLINK_CAPABILITY2_cross_link_sup(unsigned int ucross_link_sup);
int iSetLINK_CAPABILITY2_link_speed_sup(unsigned int ulink_speed_sup);
int iSetLINK_CTRL_STATUS2_drs_msg_recved(unsigned int udrs_msg_recved);
int iSetLINK_CTRL_STATUS2_downstream_component_presence(unsigned int udownstream_component_presence);
int iSetLINK_CTRL_STATUS2_crosslink_resolution(unsigned int ucrosslink_resolution);
int iSetLINK_CTRL_STATUS2_retimer2_presence_detect(unsigned int uretimer2_presence_detect);
int iSetLINK_CTRL_STATUS2_retimer_presence_detect(unsigned int uretimer_presence_detect);
int iSetLINK_CTRL_STATUS2_link_8g_eq_req(unsigned int ulink_8g_eq_req);
int iSetLINK_CTRL_STATUS2_eq_8g_phase3_success(unsigned int ueq_8g_phase3_success);
int iSetLINK_CTRL_STATUS2_eq_8g_phase2_success(unsigned int ueq_8g_phase2_success);
int iSetLINK_CTRL_STATUS2_eq_8g_phase1_success(unsigned int ueq_8g_phase1_success);
int iSetLINK_CTRL_STATUS2_eq_8g_complete(unsigned int ueq_8g_complete);
int iSetLINK_CTRL_STATUS2_cur_deemp_level(unsigned int ucur_deemp_level);
int iSetLINK_CTRL_STATUS2_compliance_preset_deemp(unsigned int ucompliance_preset_deemp);
int iSetLINK_CTRL_STATUS2_compliance_sos(unsigned int ucompliance_sos);
int iSetLINK_CTRL_STATUS2_enter_mod_compliance(unsigned int uenter_mod_compliance);
int iSetLINK_CTRL_STATUS2_transmit_margin(unsigned int utransmit_margin);
int iSetLINK_CTRL_STATUS2_selectable_de_emphasis(unsigned int uselectable_de_emphasis);
int iSetLINK_CTRL_STATUS2_hw_auto_speed_dis(unsigned int uhw_auto_speed_dis);
int iSetLINK_CTRL_STATUS2_enter_compliance(unsigned int uenter_compliance);
int iSetLINK_CTRL_STATUS2_target_link_speed(unsigned int utarget_link_speed);
int iSetSLOT_CAP_2_slot_cap_2(unsigned int uslot_cap_2);
int iSetSLOT_CTRL_2_slot_ctrl_2(unsigned int uslot_ctrl_2);
int iSetMSI_CAP_HEADER_msi_pvm_enable(unsigned int umsi_pvm_enable);
int iSetMSI_CAP_HEADER_msi_64bit_enable(unsigned int umsi_64bit_enable);
int iSetMSI_CAP_HEADER_msi_mult_msg_enable(unsigned int umsi_mult_msg_enable);
int iSetMSI_CAP_HEADER_msi_mult_msg_cap(unsigned int umsi_mult_msg_cap);
int iSetMSI_CAP_HEADER_msi_enable(unsigned int umsi_enable);
int iSetMSI_CAP_HEADER_msi_next_cap_addr(unsigned int umsi_next_cap_addr);
int iSetMSI_CAP_HEADER_msi_cap_id(unsigned int umsi_cap_id);
int iSetMSI_LADDR_msi_laddr(unsigned int umsi_laddr);
int iSetMSI_HADDR_msi_uaddr(unsigned int umsi_uaddr);
int iSetMSI_DATA_msi_data(unsigned int umsi_data);
int iSetMSI_MASK_msi_mask(unsigned int umsi_mask);
int iSetMSI_PENDING_msi_pending(unsigned int umsi_pending);
int iSetPME_CAP_HEADER_pme_support(unsigned int upme_support);
int iSetPME_CAP_HEADER_d2_support(unsigned int ud2_support);
int iSetPME_CAP_HEADER_d1_support(unsigned int ud1_support);
int iSetPME_CAP_HEADER_aux_current(unsigned int uaux_current);
int iSetPME_CAP_HEADER_device_spec_ini(unsigned int udevice_spec_ini);
int iSetPME_CAP_HEADER_immediate_rn_return_d0(unsigned int uimmediate_rn_return_d0);
int iSetPME_CAP_HEADER_pme_clk(unsigned int upme_clk);
int iSetPME_CAP_HEADER_pme_vesion(unsigned int upme_vesion);
int iSetPME_CAP_HEADER_pwr_next_ptr(unsigned int upwr_next_ptr);
int iSetPME_CAP_HEADER_pwr_capability_id(unsigned int upwr_capability_id);
int iSetPME_STATUS_pme_data(unsigned int upme_data);
int iSetPME_STATUS_bpcc_en(unsigned int ubpcc_en);
int iSetPME_STATUS_b2_b3_n(unsigned int ub2_b3_n);
int iSetPME_STATUS_pme_status(unsigned int upme_status);
int iSetPME_STATUS_data_scale(unsigned int udata_scale);
int iSetPME_STATUS_data_sel(unsigned int udata_sel);
int iSetPME_STATUS_pme_en(unsigned int upme_en);
int iSetPME_STATUS_no_soft_reset(unsigned int uno_soft_reset);
int iSetPME_STATUS_pwr_status(unsigned int upwr_status);
int iSetSID_CAP_HEADER_sid_next_cap_addr(unsigned int usid_next_cap_addr);
int iSetSID_CAP_HEADER_sid_cap_id(unsigned int usid_cap_id);
int iSetSSVID_SSID_ssid(unsigned int ussid);
int iSetSSVID_SSID_ssvid(unsigned int ussvid);
int iSetAER_CAP_HEADER_aer_next_cap_addr(unsigned int uaer_next_cap_addr);
int iSetAER_CAP_HEADER_aercapabilityversion(unsigned int uaercapabilityversion);
int iSetAER_CAP_HEADER_aercapabilityid(unsigned int uaercapabilityid);
int iSetUNCR_ERR_STATUS_poisoned_tlp_egress_blk_err_st(unsigned int upoisoned_tlp_egress_blk_err_st);
int iSetUNCR_ERR_STATUS_tlp_pfx_blk_err_st(unsigned int utlp_pfx_blk_err_st);
int iSetUNCR_ERR_STATUS_atomicop_eg_blk_st(unsigned int uatomicop_eg_blk_st);
int iSetUNCR_ERR_STATUS_mc_blk_st(unsigned int umc_blk_st);
int iSetUNCR_ERR_STATUS_uncor_int_err_st(unsigned int uuncor_int_err_st);
int iSetUNCR_ERR_STATUS_acs_vio_st(unsigned int uacs_vio_st);
int iSetUNCR_ERR_STATUS_ur_err_st(unsigned int uur_err_st);
int iSetUNCR_ERR_STATUS_ecrc_err_st(unsigned int uecrc_err_st);
int iSetUNCR_ERR_STATUS_mal_tlp_st(unsigned int umal_tlp_st);
int iSetUNCR_ERR_STATUS_rcv_overflow_st(unsigned int urcv_overflow_st);
int iSetUNCR_ERR_STATUS_unexp_cpl_st(unsigned int uunexp_cpl_st);
int iSetUNCR_ERR_STATUS_cpl_abort_st(unsigned int ucpl_abort_st);
int iSetUNCR_ERR_STATUS_cpl_timeeout_st(unsigned int ucpl_timeeout_st);
int iSetUNCR_ERR_STATUS_fc_protocol_err_st(unsigned int ufc_protocol_err_st);
int iSetUNCR_ERR_STATUS_poisoned_tlp_st(unsigned int upoisoned_tlp_st);
int iSetUNCR_ERR_STATUS_sur_down_err_st(unsigned int usur_down_err_st);
int iSetUNCR_ERR_STATUS_dl_protocal_err_st(unsigned int udl_protocal_err_st);
int iSetUNCR_ERR_STATUS_undefined_4(unsigned int uundefined_4);
int iSetUNCR_ERR_MASK_poisoned_tlp_egress_blk_err_mask(unsigned int upoisoned_tlp_egress_blk_err_mask);
int iSetUNCR_ERR_MASK_tlp_pfx_blk_err_mask(unsigned int utlp_pfx_blk_err_mask);
int iSetUNCR_ERR_MASK_atomicop_eg_blk_mask(unsigned int uatomicop_eg_blk_mask);
int iSetUNCR_ERR_MASK_mc_blk_mask(unsigned int umc_blk_mask);
int iSetUNCR_ERR_MASK_uncor_int_err_mask(unsigned int uuncor_int_err_mask);
int iSetUNCR_ERR_MASK_acs_vio_mask(unsigned int uacs_vio_mask);
int iSetUNCR_ERR_MASK_ur_err_mask(unsigned int uur_err_mask);
int iSetUNCR_ERR_MASK_ecrc_err_mask(unsigned int uecrc_err_mask);
int iSetUNCR_ERR_MASK_mal_tlp_mask(unsigned int umal_tlp_mask);
int iSetUNCR_ERR_MASK_rcv_overflow_mask(unsigned int urcv_overflow_mask);
int iSetUNCR_ERR_MASK_unexp_cpl_mask(unsigned int uunexp_cpl_mask);
int iSetUNCR_ERR_MASK_cpl_abort_mask(unsigned int ucpl_abort_mask);
int iSetUNCR_ERR_MASK_cpl_timeeout_mask(unsigned int ucpl_timeeout_mask);
int iSetUNCR_ERR_MASK_fc_protocol_err_mask(unsigned int ufc_protocol_err_mask);
int iSetUNCR_ERR_MASK_poisoned_tlp_mask(unsigned int upoisoned_tlp_mask);
int iSetUNCR_ERR_MASK_sur_down_err_mask(unsigned int usur_down_err_mask);
int iSetUNCR_ERR_MASK_dl_protocal_err_mask(unsigned int udl_protocal_err_mask);
int iSetUNCR_ERR_MASK_undefined_8(unsigned int uundefined_8);
int iSetUNCR_ERR_SEVERITY_poisoned_tlp_egress_blk_err_ser(unsigned int upoisoned_tlp_egress_blk_err_ser);
int iSetUNCR_ERR_SEVERITY_tlp_pfx_blk_err_ser(unsigned int utlp_pfx_blk_err_ser);
int iSetUNCR_ERR_SEVERITY_atomicop_eg_blk_ser(unsigned int uatomicop_eg_blk_ser);
int iSetUNCR_ERR_SEVERITY_mc_blk_ser(unsigned int umc_blk_ser);
int iSetUNCR_ERR_SEVERITY_uncor_int_err_ser(unsigned int uuncor_int_err_ser);
int iSetUNCR_ERR_SEVERITY_acs_vio_ser(unsigned int uacs_vio_ser);
int iSetUNCR_ERR_SEVERITY_ur_err_ser(unsigned int uur_err_ser);
int iSetUNCR_ERR_SEVERITY_ecrc_err_ser(unsigned int uecrc_err_ser);
int iSetUNCR_ERR_SEVERITY_mal_tlp_ser(unsigned int umal_tlp_ser);
int iSetUNCR_ERR_SEVERITY_rcv_overflow_ser(unsigned int urcv_overflow_ser);
int iSetUNCR_ERR_SEVERITY_unexp_cpl_ser(unsigned int uunexp_cpl_ser);
int iSetUNCR_ERR_SEVERITY_cpl_abort_ser(unsigned int ucpl_abort_ser);
int iSetUNCR_ERR_SEVERITY_cpl_timeeout_ser(unsigned int ucpl_timeeout_ser);
int iSetUNCR_ERR_SEVERITY_fc_protocol_err_ser(unsigned int ufc_protocol_err_ser);
int iSetUNCR_ERR_SEVERITY_poisoned_tlp_ser(unsigned int upoisoned_tlp_ser);
int iSetUNCR_ERR_SEVERITY_sur_down_err_ser(unsigned int usur_down_err_ser);
int iSetUNCR_ERR_SEVERITY_dl_protocal_err_ser(unsigned int udl_protocal_err_ser);
int iSetUNCR_ERR_SEVERITY_undefined_c(unsigned int uundefined_c);
int iSetCOR_ERR_STATUS_header_log_overflow_st(unsigned int uheader_log_overflow_st);
int iSetCOR_ERR_STATUS_cor_int_err_st(unsigned int ucor_int_err_st);
int iSetCOR_ERR_STATUS_advisory_non_fatal_err_st(unsigned int uadvisory_non_fatal_err_st);
int iSetCOR_ERR_STATUS_reply_timer_timout_st(unsigned int ureply_timer_timout_st);
int iSetCOR_ERR_STATUS_reply_num_rollover_st(unsigned int ureply_num_rollover_st);
int iSetCOR_ERR_STATUS_bad_dllp_st(unsigned int ubad_dllp_st);
int iSetCOR_ERR_STATUS_bad_tlp_st(unsigned int ubad_tlp_st);
int iSetCOR_ERR_STATUS_rx_err_st(unsigned int urx_err_st);
int iSetCOR_ERR_MASK_header_log_overflow_mask(unsigned int uheader_log_overflow_mask);
int iSetCOR_ERR_MASK_cor_int_err_mask(unsigned int ucor_int_err_mask);
int iSetCOR_ERR_MASK_advisory_non_fatal_err_mask(unsigned int uadvisory_non_fatal_err_mask);
int iSetCOR_ERR_MASK_reply_timer_timout_mask(unsigned int ureply_timer_timout_mask);
int iSetCOR_ERR_MASK_reply_num_rollover_mask(unsigned int ureply_num_rollover_mask);
int iSetCOR_ERR_MASK_bad_dllp_mask(unsigned int ubad_dllp_mask);
int iSetCOR_ERR_MASK_bad_tlp_mask(unsigned int ubad_tlp_mask);
int iSetCOR_ERR_MASK_rx_err_mask(unsigned int urx_err_mask);
int iSetADVACD_CAP_CTRL_cmp_timeout_log_cap(unsigned int ucmp_timeout_log_cap);
int iSetADVACD_CAP_CTRL_tlp_prefix_log_pre(unsigned int utlp_prefix_log_pre);
int iSetADVACD_CAP_CTRL_multi_hdr_rec_enable(unsigned int umulti_hdr_rec_enable);
int iSetADVACD_CAP_CTRL_multi_hdr_rec_cap(unsigned int umulti_hdr_rec_cap);
int iSetADVACD_CAP_CTRL_ecrc_check_en(unsigned int uecrc_check_en);
int iSetADVACD_CAP_CTRL_ecrc_check_cap(unsigned int uecrc_check_cap);
int iSetADVACD_CAP_CTRL_ecrc_gen_en(unsigned int uecrc_gen_en);
int iSetADVACD_CAP_CTRL_ecrc_gen_cap(unsigned int uecrc_gen_cap);
int iSetADVACD_CAP_CTRL_first_err_ptr(unsigned int ufirst_err_ptr);
int iSetFIRST_HEADER_LOG_first_header_log(unsigned int ufirst_header_log);
int iSetSECOND_HEADER_LOG_second_header_log(unsigned int usecond_header_log);
int iSetTHIRD_HEADER_LOG_third_header_log(unsigned int uthird_header_log);
int iSetFOUR_HEADER_LOG_four_header_log(unsigned int ufour_header_log);
int iSetROOT_ERROR_COMMAND_fatal_err_en(unsigned int ufatal_err_en);
int iSetROOT_ERROR_COMMAND_non_fatal_err_en(unsigned int unon_fatal_err_en);
int iSetROOT_ERROR_COMMAND_cor_err_en(unsigned int ucor_err_en);
int iSetROOT_ERROR_STATUS_aer_int_number(unsigned int uaer_int_number);
int iSetROOT_ERROR_STATUS_fatal_msg_rcv(unsigned int ufatal_msg_rcv);
int iSetROOT_ERROR_STATUS_non_fatal_msg_rcv(unsigned int unon_fatal_msg_rcv);
int iSetROOT_ERROR_STATUS_first_uncor_err(unsigned int ufirst_uncor_err);
int iSetROOT_ERROR_STATUS_multi_uncor_err_rcv(unsigned int umulti_uncor_err_rcv);
int iSetROOT_ERROR_STATUS_uncor_err_rcv(unsigned int uuncor_err_rcv);
int iSetROOT_ERROR_STATUS_multi_cor_err_rcv(unsigned int umulti_cor_err_rcv);
int iSetROOT_ERROR_STATUS_core_err_rcv(unsigned int ucore_err_rcv);
int iSetERR_SOURCE_IDEN_err_non_cir_source(unsigned int uerr_non_cir_source);
int iSetERR_SOURCE_IDEN_err_cor_source(unsigned int uerr_cor_source);
int iSetFIRST_PREFIX_LOG_first_prefix_log(unsigned int ufirst_prefix_log);
int iSetSECOND_PREFIX_LOG_second_prefix_log(unsigned int usecond_prefix_log);
int iSetTHIRD_PREFIX_LOG_third_prefix_log(unsigned int uthird_prefix_log);
int iSetFOUR_PREFIX_LOG_four_prefix_log(unsigned int ufour_prefix_log);
int iSetTPH_EXTEND_CAP_tph_next_cap_offset(unsigned int utph_next_cap_offset);
int iSetTPH_EXTEND_CAP_tph_cap_version(unsigned int utph_cap_version);
int iSetTPH_EXTEND_CAP_tph_extend_cap_id(unsigned int utph_extend_cap_id);
int iSetTPH_REQ_CAP_st_table_size(unsigned int ust_table_size);
int iSetTPH_REQ_CAP_st_table_location(unsigned int ust_table_location);
int iSetTPH_REQ_CAP_extend_tph_req_support(unsigned int uextend_tph_req_support);
int iSetTPH_REQ_CAP_device_spc_mode_support(unsigned int udevice_spc_mode_support);
int iSetTPH_REQ_CAP_int_vector_mode_support(unsigned int uint_vector_mode_support);
int iSetTPH_REQ_CAP_no_st_mode_support(unsigned int uno_st_mode_support);
int iSetTPH_REQ_CTRL_tph_req_enable(unsigned int utph_req_enable);
int iSetTPH_REQ_CTRL_st_mode_sel(unsigned int ust_mode_sel);
int iSetSECONDARY_PCIE_EXT_CAP_HED_sec_pcie_next_cap_offset(unsigned int usec_pcie_next_cap_offset);
int iSetSECONDARY_PCIE_EXT_CAP_HED_sec_pcie_cap_version(unsigned int usec_pcie_cap_version);
int iSetSECONDARY_PCIE_EXT_CAP_HED_sec_pcie_ext_cap_id(unsigned int usec_pcie_ext_cap_id);
int iSetLINK_CONTROL3_REGISTER_sec_pcie_lower_skp_en(unsigned int usec_pcie_lower_skp_en);
int iSetLINK_CONTROL3_REGISTER_sec_pcie_link_equaliz_req_int_en(unsigned int usec_pcie_link_equaliz_req_int_en);
int iSetLINK_CONTROL3_REGISTER_sec_pcie_perform_equaliz(unsigned int usec_pcie_perform_equaliz);
int iSetLANE_ERROR_STATUS_REG_sec_pcie_lane_err_staus(unsigned int usec_pcie_lane_err_staus);
int iSetLINK_CONTROL3_REGISTER01_sec_pcie_8g_ln1_up_rx_preset_hint(unsigned int usec_pcie_8g_ln1_up_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER01_sec_pcie_8g_ln1_up_tx_preset(unsigned int usec_pcie_8g_ln1_up_tx_preset);
int iSetLINK_CONTROL3_REGISTER01_sec_pcie_8g_ln1_dp_rx_preset_hint(unsigned int usec_pcie_8g_ln1_dp_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER01_sec_pcie_8g_ln1_dp_tx_preset(unsigned int usec_pcie_8g_ln1_dp_tx_preset);
int iSetLINK_CONTROL3_REGISTER01_sec_pcie_8g_ln0_up_rx_preset_hint(unsigned int usec_pcie_8g_ln0_up_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER01_sec_pcie_8g_ln0_up_tx_preset(unsigned int usec_pcie_8g_ln0_up_tx_preset);
int iSetLINK_CONTROL3_REGISTER01_sec_pcie_8g_ln0_dp_rx_preset_hint(unsigned int usec_pcie_8g_ln0_dp_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER01_sec_pcie_8g_ln0_dp_tx_preset(unsigned int usec_pcie_8g_ln0_dp_tx_preset);
int iSetLINK_CONTROL3_REGISTER23_sec_pcie_8g_ln3_up_rx_preset_hint(unsigned int usec_pcie_8g_ln3_up_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER23_sec_pcie_8g_ln3_up_tx_preset(unsigned int usec_pcie_8g_ln3_up_tx_preset);
int iSetLINK_CONTROL3_REGISTER23_sec_pcie_8g_ln3_dp_rx_preset_hint(unsigned int usec_pcie_8g_ln3_dp_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER23_sec_pcie_8g_ln3_dp_tx_preset(unsigned int usec_pcie_8g_ln3_dp_tx_preset);
int iSetLINK_CONTROL3_REGISTER23_sec_pcie_8g_ln2_up_rx_preset_hint(unsigned int usec_pcie_8g_ln2_up_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER23_sec_pcie_8g_ln2_up_tx_preset(unsigned int usec_pcie_8g_ln2_up_tx_preset);
int iSetLINK_CONTROL3_REGISTER23_sec_pcie_8g_ln2_dp_rx_preset_hint(unsigned int usec_pcie_8g_ln2_dp_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER23_sec_pcie_8g_ln2_dp_tx_preset(unsigned int usec_pcie_8g_ln2_dp_tx_preset);
int iSetLINK_CONTROL3_REGISTER45_sec_pcie_8g_ln5_up_rx_preset_hint(unsigned int usec_pcie_8g_ln5_up_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER45_sec_pcie_8g_ln5_up_tx_preset(unsigned int usec_pcie_8g_ln5_up_tx_preset);
int iSetLINK_CONTROL3_REGISTER45_sec_pcie_8g_ln5_dp_rx_preset_hint(unsigned int usec_pcie_8g_ln5_dp_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER45_sec_pcie_8g_ln5_dp_tx_preset(unsigned int usec_pcie_8g_ln5_dp_tx_preset);
int iSetLINK_CONTROL3_REGISTER45_sec_pcie_8g_ln4_up_rx_preset_hint(unsigned int usec_pcie_8g_ln4_up_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER45_sec_pcie_8g_ln4_up_tx_preset(unsigned int usec_pcie_8g_ln4_up_tx_preset);
int iSetLINK_CONTROL3_REGISTER45_sec_pcie_8g_ln4_dp_rx_preset_hint(unsigned int usec_pcie_8g_ln4_dp_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER45_sec_pcie_8g_ln4_dp_tx_preset(unsigned int usec_pcie_8g_ln4_dp_tx_preset);
int iSetLINK_CONTROL3_REGISTER67_sec_pcie_8g_ln7_up_rx_preset_hint(unsigned int usec_pcie_8g_ln7_up_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER67_sec_pcie_8g_ln7_up_tx_preset(unsigned int usec_pcie_8g_ln7_up_tx_preset);
int iSetLINK_CONTROL3_REGISTER67_sec_pcie_8g_ln7_dp_rx_preset_hint(unsigned int usec_pcie_8g_ln7_dp_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER67_sec_pcie_8g_ln7_dp_tx_preset(unsigned int usec_pcie_8g_ln7_dp_tx_preset);
int iSetLINK_CONTROL3_REGISTER67_sec_pcie_8g_ln6_up_rx_preset_hint(unsigned int usec_pcie_8g_ln6_up_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER67_sec_pcie_8g_ln6_up_tx_preset(unsigned int usec_pcie_8g_ln6_up_tx_preset);
int iSetLINK_CONTROL3_REGISTER67_sec_pcie_8g_ln6_dp_rx_preset_hint(unsigned int usec_pcie_8g_ln6_dp_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER67_sec_pcie_8g_ln6_dp_tx_preset(unsigned int usec_pcie_8g_ln6_dp_tx_preset);
int iSetLINK_CONTROL3_REGISTER89_sec_pcie_8g_ln9_up_rx_preset_hint(unsigned int usec_pcie_8g_ln9_up_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER89_sec_pcie_8g_ln9_up_tx_preset(unsigned int usec_pcie_8g_ln9_up_tx_preset);
int iSetLINK_CONTROL3_REGISTER89_sec_pcie_8g_ln9_dp_rx_preset_hint(unsigned int usec_pcie_8g_ln9_dp_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER89_sec_pcie_8g_ln9_dp_tx_preset(unsigned int usec_pcie_8g_ln9_dp_tx_preset);
int iSetLINK_CONTROL3_REGISTER89_sec_pcie_8g_ln8_up_rx_preset_hint(unsigned int usec_pcie_8g_ln8_up_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER89_sec_pcie_8g_ln8_up_tx_preset(unsigned int usec_pcie_8g_ln8_up_tx_preset);
int iSetLINK_CONTROL3_REGISTER89_sec_pcie_8g_ln8_dp_rx_preset_hint(unsigned int usec_pcie_8g_ln8_dp_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER89_sec_pcie_8g_ln8_dp_tx_preset(unsigned int usec_pcie_8g_ln8_dp_tx_preset);
int iSetLINK_CONTROL3_REGISTER1011_sec_pcie_8g_ln11_up_rx_preset_hint(unsigned int usec_pcie_8g_ln11_up_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER1011_sec_pcie_8g_ln11_up_tx_preset(unsigned int usec_pcie_8g_ln11_up_tx_preset);
int iSetLINK_CONTROL3_REGISTER1011_sec_pcie_8g_ln11_dp_rx_preset_hint(unsigned int usec_pcie_8g_ln11_dp_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER1011_sec_pcie_8g_ln11_dp_tx_preset(unsigned int usec_pcie_8g_ln11_dp_tx_preset);
int iSetLINK_CONTROL3_REGISTER1011_sec_pcie_8g_ln10_up_rx_preset_hint(unsigned int usec_pcie_8g_ln10_up_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER1011_sec_pcie_8g_ln10_up_tx_preset(unsigned int usec_pcie_8g_ln10_up_tx_preset);
int iSetLINK_CONTROL3_REGISTER1011_sec_pcie_8g_ln10_dp_rx_preset_hint(unsigned int usec_pcie_8g_ln10_dp_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER1011_sec_pcie_8g_ln10_dp_tx_preset(unsigned int usec_pcie_8g_ln10_dp_tx_preset);
int iSetLINK_CONTROL3_REGISTER1213_sec_pcie_8g_ln13_up_rx_preset_hint(unsigned int usec_pcie_8g_ln13_up_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER1213_sec_pcie_8g_ln13_up_tx_preset(unsigned int usec_pcie_8g_ln13_up_tx_preset);
int iSetLINK_CONTROL3_REGISTER1213_sec_pcie_8g_ln13_dp_rx_preset_hint(unsigned int usec_pcie_8g_ln13_dp_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER1213_sec_pcie_8g_ln13_dp_tx_preset(unsigned int usec_pcie_8g_ln13_dp_tx_preset);
int iSetLINK_CONTROL3_REGISTER1213_sec_pcie_8g_ln12_up_rx_preset_hint(unsigned int usec_pcie_8g_ln12_up_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER1213_sec_pcie_8g_ln12_up_tx_preset(unsigned int usec_pcie_8g_ln12_up_tx_preset);
int iSetLINK_CONTROL3_REGISTER1213_sec_pcie_8g_ln12_dp_rx_preset_hint(unsigned int usec_pcie_8g_ln12_dp_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER1213_sec_pcie_8g_ln12_dp_tx_preset(unsigned int usec_pcie_8g_ln12_dp_tx_preset);
int iSetLINK_CONTROL3_REGISTER1415_sec_pcie_8g_ln15_up_rx_preset_hint(unsigned int usec_pcie_8g_ln15_up_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER1415_sec_pcie_8g_ln15_up_tx_preset(unsigned int usec_pcie_8g_ln15_up_tx_preset);
int iSetLINK_CONTROL3_REGISTER1415_sec_pcie_8g_ln15_dp_rx_preset_hint(unsigned int usec_pcie_8g_ln15_dp_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER1415_sec_pcie_8g_ln15_dp_tx_preset(unsigned int usec_pcie_8g_ln15_dp_tx_preset);
int iSetLINK_CONTROL3_REGISTER1415_sec_pcie_8g_ln14_up_rx_preset_hint(unsigned int usec_pcie_8g_ln14_up_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER1415_sec_pcie_8g_ln14_up_tx_preset(unsigned int usec_pcie_8g_ln14_up_tx_preset);
int iSetLINK_CONTROL3_REGISTER1415_sec_pcie_8g_ln14_dp_rx_preset_hint(unsigned int usec_pcie_8g_ln14_dp_rx_preset_hint);
int iSetLINK_CONTROL3_REGISTER1415_sec_pcie_8g_ln14_dp_tx_preset(unsigned int usec_pcie_8g_ln14_dp_tx_preset);
int iSetVC_CAP_0X00_vc_next_cap_offset(unsigned int uvc_next_cap_offset);
int iSetVC_CAP_0X00_vc_cap_version(unsigned int uvc_cap_version);
int iSetVC_CAP_0X00_vc_cap_id(unsigned int uvc_cap_id);
int iSetVC_CAP_0X04_vc_func_arb_table_size(unsigned int uvc_func_arb_table_size);
int iSetVC_CAP_0X04_vc_ref_clk(unsigned int uvc_ref_clk);
int iSetVC_CAP_0X04_vc_low_pri_ext_vc_count(unsigned int uvc_low_pri_ext_vc_count);
int iSetVC_CAP_0X04_vc_ext_vc_count(unsigned int uvc_ext_vc_count);
int iSetVC_CAP_0X08_vc_vc_arb_table_offset(unsigned int uvc_vc_arb_table_offset);
int iSetVC_CAP_0X08_vc_vc_arb_cap(unsigned int uvc_vc_arb_cap);
int iSetVC_CAP_0X0C_vc_vc_table_status(unsigned int uvc_vc_table_status);
int iSetVC_CAP_0X0C_vc_vc_arb_sel(unsigned int uvc_vc_arb_sel);
int iSetVC_CAP_0X0C_vc_load_vc_arb_table(unsigned int uvc_load_vc_arb_table);
int iSetVC_CAP_0X10_vc0_port_arb_table_offset(unsigned int uvc0_port_arb_table_offset);
int iSetVC_CAP_0X10_vc0_max_time_slot(unsigned int uvc0_max_time_slot);
int iSetVC_CAP_0X10_vc0_reject_snoop_trs(unsigned int uvc0_reject_snoop_trs);
int iSetVC_CAP_0X10_vc10_undefined(unsigned int uvc10_undefined);
int iSetVC_CAP_0X10_vc0_port_arb_cap(unsigned int uvc0_port_arb_cap);
int iSetVC_CAP_0X14_vc0_enable(unsigned int uvc0_enable);
int iSetVC_CAP_0X14_vc0_vc_id(unsigned int uvc0_vc_id);
int iSetVC_CAP_0X14_vc0_port_arb_sel(unsigned int uvc0_port_arb_sel);
int iSetVC_CAP_0X14_vc0_load_port_arb_table(unsigned int uvc0_load_port_arb_table);
int iSetVC_CAP_0X14_vc0_tc_vc_map(unsigned int uvc0_tc_vc_map);
int iSetVC_CAP_0X18_vc0_negoti_pending(unsigned int uvc0_negoti_pending);
int iSetVC_CAP_0X18_vc0_port_arb_table_status(unsigned int uvc0_port_arb_table_status);
int iSetVC_CAP_0X1C_vc1_port_arb_table_offset(unsigned int uvc1_port_arb_table_offset);
int iSetVC_CAP_0X1C_vc1_max_time_slot(unsigned int uvc1_max_time_slot);
int iSetVC_CAP_0X1C_vc1_reject_snoop_trs(unsigned int uvc1_reject_snoop_trs);
int iSetVC_CAP_0X1C_vc1c_undefined(unsigned int uvc1c_undefined);
int iSetVC_CAP_0X1C_vc1_port_arb_cap(unsigned int uvc1_port_arb_cap);
int iSetVC_CAP_0X20_vc1_enable(unsigned int uvc1_enable);
int iSetVC_CAP_0X20_vc1_vc_id(unsigned int uvc1_vc_id);
int iSetVC_CAP_0X20_vc1_port_arb_sel(unsigned int uvc1_port_arb_sel);
int iSetVC_CAP_0X20_vc1_load_port_arb_table(unsigned int uvc1_load_port_arb_table);
int iSetVC_CAP_0X20_vc1_tc_vc_map(unsigned int uvc1_tc_vc_map);
int iSetVC_CAP_0X24_vc1_negoti_pending(unsigned int uvc1_negoti_pending);
int iSetVC_CAP_0X24_vc1_port_arb_table_status(unsigned int uvc1_port_arb_table_status);
int iSetDEVICE_SERIAL_NUMBER_CAP_HEADER_dsn_next_cap_offset(unsigned int udsn_next_cap_offset);
int iSetDEVICE_SERIAL_NUMBER_CAP_HEADER_dsn_cap_version(unsigned int udsn_cap_version);
int iSetDEVICE_SERIAL_NUMBER_CAP_HEADER_dsn_extend_cap(unsigned int udsn_extend_cap);
int iSetSERIAL_LNUM_dsn_1st_dw(unsigned int udsn_1st_dw);
int iSetSERIAL_HNUM_dsn_2nd_dw(unsigned int udsn_2nd_dw);
int iSetACS_CAP_0X00_acs_cap_next_cap_addr(unsigned int uacs_cap_next_cap_addr);
int iSetACS_CAP_0X00_acs_cap_version(unsigned int uacs_cap_version);
int iSetACS_CAP_0X00_acs_capid(unsigned int uacs_capid);
int iSetACS_CAP_0X04_acs_direct_tx_p2p_en(unsigned int uacs_direct_tx_p2p_en);
int iSetACS_CAP_0X04_acs_p2p_egress_ctrl_en(unsigned int uacs_p2p_egress_ctrl_en);
int iSetACS_CAP_0X04_acs_up_forward_en(unsigned int uacs_up_forward_en);
int iSetACS_CAP_0X04_acs_p2p_cpl_redirect_en(unsigned int uacs_p2p_cpl_redirect_en);
int iSetACS_CAP_0X04_acs_p2p_req_redirect_en(unsigned int uacs_p2p_req_redirect_en);
int iSetACS_CAP_0X04_acs_tx_block_en(unsigned int uacs_tx_block_en);
int iSetACS_CAP_0X04_acs_src_vld_en(unsigned int uacs_src_vld_en);
int iSetACS_CAP_0X04_acs_ctrl_vec_size(unsigned int uacs_ctrl_vec_size);
int iSetACS_CAP_0X04_acs_direct_tx_p2p(unsigned int uacs_direct_tx_p2p);
int iSetACS_CAP_0X04_acs_p2p_egress_ctrl(unsigned int uacs_p2p_egress_ctrl);
int iSetACS_CAP_0X04_acs_up_forward(unsigned int uacs_up_forward);
int iSetACS_CAP_0X04_acs_p2p_cpl_redirect(unsigned int uacs_p2p_cpl_redirect);
int iSetACS_CAP_0X04_acs_p2p_req_redirect(unsigned int uacs_p2p_req_redirect);
int iSetACS_CAP_0X04_acs_tx_block(unsigned int uacs_tx_block);
int iSetACS_CAP_0X04_acs_src_vld(unsigned int uacs_src_vld);
int iSetDPC_CAP_0X00_dpc_next_offset(unsigned int udpc_next_offset);
int iSetDPC_CAP_0X00_dpc_cap_ver(unsigned int udpc_cap_ver);
int iSetDPC_CAP_0X00_dpc_cap_id(unsigned int udpc_cap_id);
int iSetDPC_CAP_0X04_dl_active_err_cor_en(unsigned int udl_active_err_cor_en);
int iSetDPC_CAP_0X04_dpc_soft_trig(unsigned int udpc_soft_trig);
int iSetDPC_CAP_0X04_ep_egress_blk_en(unsigned int uep_egress_blk_en);
int iSetDPC_CAP_0X04_dpc_err_cor_en(unsigned int udpc_err_cor_en);
int iSetDPC_CAP_0X04_dpc_int_en(unsigned int udpc_int_en);
int iSetDPC_CAP_0X04_dpc_cpl_ctrl(unsigned int udpc_cpl_ctrl);
int iSetDPC_CAP_0X04_dp_trig_en(unsigned int udp_trig_en);
int iSetDPC_CAP_0X04_dl_active_signal_sup(unsigned int udl_active_signal_sup);
int iSetDPC_CAP_0X04_pio_log_size(unsigned int upio_log_size);
int iSetDPC_CAP_0X04_soft_trig_sup(unsigned int usoft_trig_sup);
int iSetDPC_CAP_0X04_egress_block_ep_tlp_sup(unsigned int uegress_block_ep_tlp_sup);
int iSetDPC_CAP_0X04_ext_for_dpc(unsigned int uext_for_dpc);
int iSetDPC_CAP_0X04_dcp_int_msg_num(unsigned int udcp_int_msg_num);
int iSetDPC_CAP_0X08_dpc_err_src_id(unsigned int udpc_err_src_id);
int iSetDPC_CAP_0X08_rp_pio_1st_ptr(unsigned int urp_pio_1st_ptr);
int iSetDPC_CAP_0X08_dpc_trig_reason_ext(unsigned int udpc_trig_reason_ext);
int iSetDPC_CAP_0X08_dpc_rp_busy(unsigned int udpc_rp_busy);
int iSetDPC_CAP_0X08_dpc_int_sts(unsigned int udpc_int_sts);
int iSetDPC_CAP_0X08_dpc_trig_reason(unsigned int udpc_trig_reason);
int iSetDPC_CAP_0X08_dpc_trig_sts(unsigned int udpc_trig_sts);
int iSetDPC_CAP_0X0C_mem_cto(unsigned int umem_cto);
int iSetDPC_CAP_0X0C_mem_ca(unsigned int umem_ca);
int iSetDPC_CAP_0X0C_mem_ur(unsigned int umem_ur);
int iSetDPC_CAP_0X0C_io_cto(unsigned int uio_cto);
int iSetDPC_CAP_0X0C_io_ca(unsigned int uio_ca);
int iSetDPC_CAP_0X0C_io_ur(unsigned int uio_ur);
int iSetDPC_CAP_0X0C_cfg_cto(unsigned int ucfg_cto);
int iSetDPC_CAP_0X0C_cfg_ca(unsigned int ucfg_ca);
int iSetDPC_CAP_0X0C_cfg_ur(unsigned int ucfg_ur);
int iSetDPC_CAP_0X10_mem_cto_mask(unsigned int umem_cto_mask);
int iSetDPC_CAP_0X10_mem_ca_mask(unsigned int umem_ca_mask);
int iSetDPC_CAP_0X10_mem_ur_mask(unsigned int umem_ur_mask);
int iSetDPC_CAP_0X10_io_cto_mask(unsigned int uio_cto_mask);
int iSetDPC_CAP_0X10_io_ca_mask(unsigned int uio_ca_mask);
int iSetDPC_CAP_0X10_io_ur_mask(unsigned int uio_ur_mask);
int iSetDPC_CAP_0X10_cfg_cto_mask(unsigned int ucfg_cto_mask);
int iSetDPC_CAP_0X10_cfg_ca_mask(unsigned int ucfg_ca_mask);
int iSetDPC_CAP_0X10_cfg_ur_mask(unsigned int ucfg_ur_mask);
int iSetDPC_CAP_0X14_mem_cto_svr(unsigned int umem_cto_svr);
int iSetDPC_CAP_0X14_mem_ca_svr(unsigned int umem_ca_svr);
int iSetDPC_CAP_0X14_mem_ur_svr(unsigned int umem_ur_svr);
int iSetDPC_CAP_0X14_io_cto_svr(unsigned int uio_cto_svr);
int iSetDPC_CAP_0X14_io_ca_svr(unsigned int uio_ca_svr);
int iSetDPC_CAP_0X14_io_ur_svr(unsigned int uio_ur_svr);
int iSetDPC_CAP_0X14_cfg_cto_svr(unsigned int ucfg_cto_svr);
int iSetDPC_CAP_0X14_cfg_ca_svr(unsigned int ucfg_ca_svr);
int iSetDPC_CAP_0X14_cfg_ur_svr(unsigned int ucfg_ur_svr);
int iSetDPC_CAP_0X18_mem_cto_syserr(unsigned int umem_cto_syserr);
int iSetDPC_CAP_0X18_mem_ca_syserr(unsigned int umem_ca_syserr);
int iSetDPC_CAP_0X18_mem_ur_syserr(unsigned int umem_ur_syserr);
int iSetDPC_CAP_0X18_io_cto_syserr(unsigned int uio_cto_syserr);
int iSetDPC_CAP_0X18_io_ca_syserr(unsigned int uio_ca_syserr);
int iSetDPC_CAP_0X18_io_ur_syserr(unsigned int uio_ur_syserr);
int iSetDPC_CAP_0X18_cfg_cto_syserr(unsigned int ucfg_cto_syserr);
int iSetDPC_CAP_0X18_cfg_ca_syserr(unsigned int ucfg_ca_syserr);
int iSetDPC_CAP_0X18_cfg_ur_syserr(unsigned int ucfg_ur_syserr);
int iSetDPC_CAP_0X1C_mem_cto_exception(unsigned int umem_cto_exception);
int iSetDPC_CAP_0X1C_mem_ca_exception(unsigned int umem_ca_exception);
int iSetDPC_CAP_0X1C_mem_ur_exception(unsigned int umem_ur_exception);
int iSetDPC_CAP_0X1C_io_cto_exception(unsigned int uio_cto_exception);
int iSetDPC_CAP_0X1C_io_ca_exception(unsigned int uio_ca_exception);
int iSetDPC_CAP_0X1C_io_ur_exception(unsigned int uio_ur_exception);
int iSetDPC_CAP_0X1C_cfg_cto_exception(unsigned int ucfg_cto_exception);
int iSetDPC_CAP_0X1C_cfg_ca_exception(unsigned int ucfg_ca_exception);
int iSetDPC_CAP_0X1C_cfg_ur_exception(unsigned int ucfg_ur_exception);
int iSetDPC_CAP_0X20_log_hed_dw1(unsigned int ulog_hed_dw1);
int iSetDPC_CAP_0X24_log_hed_dw2(unsigned int ulog_hed_dw2);
int iSetDPC_CAP_0X28_log_hed_dw3(unsigned int ulog_hed_dw3);
int iSetDPC_CAP_0X2C_log_hed_dw4(unsigned int ulog_hed_dw4);
int iSetDPC_CAP_0X30_imspcec_log(unsigned int uimspcec_log);
int iSetDPC_CAP_0X34_prefix_log_dw1(unsigned int uprefix_log_dw1);
int iSetDPC_CAP_0X38_prefix_log_dw2(unsigned int uprefix_log_dw2);
int iSetDPC_CAP_0X3C_prefix_log_dw3(unsigned int uprefix_log_dw3);
int iSetDPC_CAP_0X40_prefix_log_dw4(unsigned int uprefix_log_dw4);
int iSetDL_FEATURE_CAP_REG00_dl_feature_cap_next_cap_addr(unsigned int udl_feature_cap_next_cap_addr);
int iSetDL_FEATURE_CAP_REG00_dl_feature_cap_version(unsigned int udl_feature_cap_version);
int iSetDL_FEATURE_CAP_REG00_dl_feature_capid(unsigned int udl_feature_capid);
int iSetDL_FEATURE_CAP_REG04_feature_exchange_en(unsigned int ufeature_exchange_en);
int iSetDL_FEATURE_CAP_REG04_local_future_feature_support(unsigned int ulocal_future_feature_support);
int iSetDL_FEATURE_CAP_REG04_local_scale_fc_support(unsigned int ulocal_scale_fc_support);
int iSetDL_FEATURE_CAP_REG08_remote_feature_sup_vld(unsigned int uremote_feature_sup_vld);
int iSetDL_FEATURE_CAP_REG08_remote_future_feature_support(unsigned int uremote_future_feature_support);
int iSetDL_FEATURE_CAP_REG08_remote_scale_fc_support(unsigned int uremote_scale_fc_support);
int iSetRXMARGIN_CAP_REG00_rxmargin_cap_next_cap_addr(unsigned int urxmargin_cap_next_cap_addr);
int iSetRXMARGIN_CAP_REG00_rxmargin_cap_version(unsigned int urxmargin_cap_version);
int iSetRXMARGIN_CAP_REG00_rxmargin_capid(unsigned int urxmargin_capid);
int iSetRXMARGIN_CAP_REG04_margin_soft_ready(unsigned int umargin_soft_ready);
int iSetRXMARGIN_CAP_REG04_margin_ready(unsigned int umargin_ready);
int iSetRXMARGIN_CAP_REG04_margin_use_driver_soft(unsigned int umargin_use_driver_soft);
int iSetRXMARGIN_CAP_REG08_margin_payload_status(unsigned int umargin_payload_status);
int iSetRXMARGIN_CAP_REG08_rsvdp_bit23(unsigned int ursvdp_bit23);
int iSetRXMARGIN_CAP_REG08_usage_model_status(unsigned int uusage_model_status);
int iSetRXMARGIN_CAP_REG08_margin_type_status(unsigned int umargin_type_status);
int iSetRXMARGIN_CAP_REG08_receiver_num_status(unsigned int ureceiver_num_status);
int iSetRXMARGIN_CAP_REG08_margin_payload(unsigned int umargin_payload);
int iSetRXMARGIN_CAP_REG08_rsvdp_bit7(unsigned int ursvdp_bit7);
int iSetRXMARGIN_CAP_REG08_usage_model(unsigned int uusage_model);
int iSetRXMARGIN_CAP_REG08_margin_type(unsigned int umargin_type);
int iSetRXMARGIN_CAP_REG08_receiver_num(unsigned int ureceiver_num);
int iSetCCIX_TS_CAP_REG00_ccix_ts_cap_next_cap_addr(unsigned int uccix_ts_cap_next_cap_addr);
int iSetCCIX_TS_CAP_REG00_ccix_ts_cap_version(unsigned int uccix_ts_cap_version);
int iSetCCIX_TS_CAP_REG00_ccix_ts_capid(unsigned int uccix_ts_capid);
int iSetCCIX_TS_CAP_REG04_dvsec_length(unsigned int udvsec_length);
int iSetCCIX_TS_CAP_REG04_dvsec_version(unsigned int udvsec_version);
int iSetCCIX_TS_CAP_REG04_dvsec_vendor_id(unsigned int udvsec_vendor_id);
int iSetCCIX_TS_CAP_REG08_esm_mode_sup(unsigned int uesm_mode_sup);
int iSetCCIX_TS_CAP_REG08_esm_cali_done(unsigned int uesm_cali_done);
int iSetCCIX_TS_CAP_REG08_esm_cur_data_rate(unsigned int uesm_cur_data_rate);
int iSetCCIX_TS_CAP_REG08_dvsec_id(unsigned int udvsec_id);
int iSetCCIX_TS_CAP_REG0C_esm_support_rate(unsigned int uesm_support_rate);

int iSetCCIX_TS_CAP_REG14_esm_enable(unsigned int uesm_enable);
int iSetCCIX_TS_CAP_REG14_esm_data_rate1(unsigned int uesm_data_rate1);
int iSetCCIX_TS_CAP_REG14_esm_perform_eq(unsigned int uesm_perform_eq);
int iSetCCIX_TS_CAP_REG14_esm_data_rate0(unsigned int uesm_data_rate0);
int iSetCCIX_TS_CAP_REG18_esm_up_20g_txpreset_lane3(unsigned int uesm_up_20g_txpreset_lane3);
int iSetCCIX_TS_CAP_REG18_esm_dp_20g_txpreset_lane3(unsigned int uesm_dp_20g_txpreset_lane3);
int iSetCCIX_TS_CAP_REG18_esm_up_20g_txpreset_lane2(unsigned int uesm_up_20g_txpreset_lane2);
int iSetCCIX_TS_CAP_REG18_esm_dp_20g_txpreset_lane2(unsigned int uesm_dp_20g_txpreset_lane2);
int iSetCCIX_TS_CAP_REG18_esm_up_20g_txpreset_lane1(unsigned int uesm_up_20g_txpreset_lane1);
int iSetCCIX_TS_CAP_REG18_esm_dp_20g_txpreset_lane1(unsigned int uesm_dp_20g_txpreset_lane1);
int iSetCCIX_TS_CAP_REG18_esm_up_20g_txpreset_lane0(unsigned int uesm_up_20g_txpreset_lane0);
int iSetCCIX_TS_CAP_REG18_esm_dp_20g_txpreset_lane0(unsigned int uesm_dp_20g_txpreset_lane0);
int iSetCCIX_TS_CAP_REG1C_esm_up_20g_txpreset_lane7(unsigned int uesm_up_20g_txpreset_lane7);
int iSetCCIX_TS_CAP_REG1C_esm_dp_20g_txpreset_lane7(unsigned int uesm_dp_20g_txpreset_lane7);
int iSetCCIX_TS_CAP_REG1C_esm_up_20g_txpreset_lane6(unsigned int uesm_up_20g_txpreset_lane6);
int iSetCCIX_TS_CAP_REG1C_esm_dp_20g_txpreset_lane6(unsigned int uesm_dp_20g_txpreset_lane6);
int iSetCCIX_TS_CAP_REG1C_esm_up_20g_txpreset_lane5(unsigned int uesm_up_20g_txpreset_lane5);
int iSetCCIX_TS_CAP_REG1C_esm_dp_20g_txpreset_lane5(unsigned int uesm_dp_20g_txpreset_lane5);
int iSetCCIX_TS_CAP_REG1C_esm_up_20g_txpreset_lane4(unsigned int uesm_up_20g_txpreset_lane4);
int iSetCCIX_TS_CAP_REG1C_esm_dp_20g_txpreset_lane4(unsigned int uesm_dp_20g_txpreset_lane4);
int iSetCCIX_TS_CAP_REG20_esm_up_20g_txpreset_lane11(unsigned int uesm_up_20g_txpreset_lane11);
int iSetCCIX_TS_CAP_REG20_esm_dp_20g_txpreset_lane11(unsigned int uesm_dp_20g_txpreset_lane11);
int iSetCCIX_TS_CAP_REG20_esm_up_20g_txpreset_lane10(unsigned int uesm_up_20g_txpreset_lane10);
int iSetCCIX_TS_CAP_REG20_esm_dp_20g_txpreset_lane10(unsigned int uesm_dp_20g_txpreset_lane10);
int iSetCCIX_TS_CAP_REG20_esm_up_20g_txpreset_lane9(unsigned int uesm_up_20g_txpreset_lane9);
int iSetCCIX_TS_CAP_REG20_esm_dp_20g_txpreset_lane9(unsigned int uesm_dp_20g_txpreset_lane9);
int iSetCCIX_TS_CAP_REG20_esm_up_20g_txpreset_lane8(unsigned int uesm_up_20g_txpreset_lane8);
int iSetCCIX_TS_CAP_REG20_esm_dp_20g_txpreset_lane8(unsigned int uesm_dp_20g_txpreset_lane8);
int iSetCCIX_TS_CAP_REG24_esm_up_20g_txpreset_lane15(unsigned int uesm_up_20g_txpreset_lane15);
int iSetCCIX_TS_CAP_REG24_esm_dp_20g_txpreset_lane15(unsigned int uesm_dp_20g_txpreset_lane15);
int iSetCCIX_TS_CAP_REG24_esm_up_20g_txpreset_lane14(unsigned int uesm_up_20g_txpreset_lane14);
int iSetCCIX_TS_CAP_REG24_esm_dp_20g_txpreset_lane14(unsigned int uesm_dp_20g_txpreset_lane14);
int iSetCCIX_TS_CAP_REG24_esm_up_20g_txpreset_lane13(unsigned int uesm_up_20g_txpreset_lane13);
int iSetCCIX_TS_CAP_REG24_esm_dp_20g_txpreset_lane13(unsigned int uesm_dp_20g_txpreset_lane13);
int iSetCCIX_TS_CAP_REG24_esm_up_20g_txpreset_lane12(unsigned int uesm_up_20g_txpreset_lane12);
int iSetCCIX_TS_CAP_REG24_esm_dp_20g_txpreset_lane12(unsigned int uesm_dp_20g_txpreset_lane12);
int iSetCCIX_TS_CAP_REG28_esm_up_25g_txpreset_lane3(unsigned int uesm_up_25g_txpreset_lane3);
int iSetCCIX_TS_CAP_REG28_esm_dp_25g_txpreset_lane3(unsigned int uesm_dp_25g_txpreset_lane3);
int iSetCCIX_TS_CAP_REG28_esm_up_25g_txpreset_lane2(unsigned int uesm_up_25g_txpreset_lane2);
int iSetCCIX_TS_CAP_REG28_esm_dp_25g_txpreset_lane2(unsigned int uesm_dp_25g_txpreset_lane2);
int iSetCCIX_TS_CAP_REG28_esm_up_25g_txpreset_lane1(unsigned int uesm_up_25g_txpreset_lane1);
int iSetCCIX_TS_CAP_REG28_esm_dp_25g_txpreset_lane1(unsigned int uesm_dp_25g_txpreset_lane1);
int iSetCCIX_TS_CAP_REG28_esm_up_25g_txpreset_lane0(unsigned int uesm_up_25g_txpreset_lane0);
int iSetCCIX_TS_CAP_REG28_esm_dp_25g_txpreset_lane0(unsigned int uesm_dp_25g_txpreset_lane0);
int iSetCCIX_TS_CAP_REG2C_esm_up_25g_txpreset_lane7(unsigned int uesm_up_25g_txpreset_lane7);
int iSetCCIX_TS_CAP_REG2C_esm_dp_25g_txpreset_lane7(unsigned int uesm_dp_25g_txpreset_lane7);
int iSetCCIX_TS_CAP_REG2C_esm_up_25g_txpreset_lane6(unsigned int uesm_up_25g_txpreset_lane6);
int iSetCCIX_TS_CAP_REG2C_esm_dp_25g_txpreset_lane6(unsigned int uesm_dp_25g_txpreset_lane6);
int iSetCCIX_TS_CAP_REG2C_esm_up_25g_txpreset_lane5(unsigned int uesm_up_25g_txpreset_lane5);
int iSetCCIX_TS_CAP_REG2C_esm_dp_25g_txpreset_lane5(unsigned int uesm_dp_25g_txpreset_lane5);
int iSetCCIX_TS_CAP_REG2C_esm_up_25g_txpreset_lane4(unsigned int uesm_up_25g_txpreset_lane4);
int iSetCCIX_TS_CAP_REG2C_esm_dp_25g_txpreset_lane4(unsigned int uesm_dp_25g_txpreset_lane4);
int iSetCCIX_TS_CAP_REG30_esm_up_25g_txpreset_lane11(unsigned int uesm_up_25g_txpreset_lane11);
int iSetCCIX_TS_CAP_REG30_esm_dp_25g_txpreset_lane11(unsigned int uesm_dp_25g_txpreset_lane11);
int iSetCCIX_TS_CAP_REG30_esm_up_25g_txpreset_lane10(unsigned int uesm_up_25g_txpreset_lane10);
int iSetCCIX_TS_CAP_REG30_esm_dp_25g_txpreset_lane10(unsigned int uesm_dp_25g_txpreset_lane10);
int iSetCCIX_TS_CAP_REG30_esm_up_25g_txpreset_lane9(unsigned int uesm_up_25g_txpreset_lane9);
int iSetCCIX_TS_CAP_REG30_esm_dp_25g_txpreset_lane9(unsigned int uesm_dp_25g_txpreset_lane9);
int iSetCCIX_TS_CAP_REG30_esm_up_25g_txpreset_lane8(unsigned int uesm_up_25g_txpreset_lane8);
int iSetCCIX_TS_CAP_REG30_esm_dp_25g_txpreset_lane8(unsigned int uesm_dp_25g_txpreset_lane8);
int iSetCCIX_TS_CAP_REG34_esm_up_25g_txpreset_lane15(unsigned int uesm_up_25g_txpreset_lane15);
int iSetCCIX_TS_CAP_REG34_esm_dp_25g_txpreset_lane15(unsigned int uesm_dp_25g_txpreset_lane15);
int iSetCCIX_TS_CAP_REG34_esm_up_25g_txpreset_lane14(unsigned int uesm_up_25g_txpreset_lane14);
int iSetCCIX_TS_CAP_REG34_esm_dp_25g_txpreset_lane14(unsigned int uesm_dp_25g_txpreset_lane14);
int iSetCCIX_TS_CAP_REG34_esm_up_25g_txpreset_lane13(unsigned int uesm_up_25g_txpreset_lane13);
int iSetCCIX_TS_CAP_REG34_esm_dp_25g_txpreset_lane13(unsigned int uesm_dp_25g_txpreset_lane13);
int iSetCCIX_TS_CAP_REG34_esm_up_25g_txpreset_lane12(unsigned int uesm_up_25g_txpreset_lane12);
int iSetCCIX_TS_CAP_REG34_esm_dp_25g_txpreset_lane12(unsigned int uesm_dp_25g_txpreset_lane12);
int iSetCCIX_TS_CAP_REG38_opt_tlp_format_sup(unsigned int uopt_tlp_format_sup);
int iSetCCIX_TS_CAP_REG3C_opt_tlp_format_en(unsigned int uopt_tlp_format_en);
int iSetGEN4_PHY_CAP_REG00_gen4_phy_cap_next_cap_addr(unsigned int ugen4_phy_cap_next_cap_addr);
int iSetGEN4_PHY_CAP_REG00_gen4_phy_cap_version(unsigned int ugen4_phy_cap_version);
int iSetGEN4_PHY_CAP_REG00_gen4_phy_capid(unsigned int ugen4_phy_capid);


int iSetGEN4_PHY_CAP_REG0C_gen4_link_equalization_req(unsigned int ugen4_link_equalization_req);
int iSetGEN4_PHY_CAP_REG0C_gen4_eq_phase3_succ(unsigned int ugen4_eq_phase3_succ);
int iSetGEN4_PHY_CAP_REG0C_gen4_eq_phase2_succ(unsigned int ugen4_eq_phase2_succ);
int iSetGEN4_PHY_CAP_REG0C_gen4_eq_phase1_succ(unsigned int ugen4_eq_phase1_succ);
int iSetGEN4_PHY_CAP_REG0C_gen4_eq_complete(unsigned int ugen4_eq_complete);
int iSetGEN4_PHY_CAP_REG10_local_data_parity_err(unsigned int ulocal_data_parity_err);
int iSetGEN4_PHY_CAP_REG14_retimer_data_parity_err(unsigned int uretimer_data_parity_err);
int iSetGEN4_PHY_CAP_REG18_retimer2_data_parity_err(unsigned int uretimer2_data_parity_err);

int iSetGEN4_PHY_CAP_REG20_gen4_lane3_up_tx_preset(unsigned int ugen4_lane3_up_tx_preset);
int iSetGEN4_PHY_CAP_REG20_gen4_lane3_dp_tx_preset(unsigned int ugen4_lane3_dp_tx_preset);
int iSetGEN4_PHY_CAP_REG20_gen4_lane2_up_tx_preset(unsigned int ugen4_lane2_up_tx_preset);
int iSetGEN4_PHY_CAP_REG20_gen4_lane2_dp_tx_preset(unsigned int ugen4_lane2_dp_tx_preset);
int iSetGEN4_PHY_CAP_REG20_gen4_lane1_up_tx_preset(unsigned int ugen4_lane1_up_tx_preset);
int iSetGEN4_PHY_CAP_REG20_gen4_lane1_dp_tx_preset(unsigned int ugen4_lane1_dp_tx_preset);
int iSetGEN4_PHY_CAP_REG20_gen4_lane0_up_tx_preset(unsigned int ugen4_lane0_up_tx_preset);
int iSetGEN4_PHY_CAP_REG20_gen4_lane0_dp_tx_preset(unsigned int ugen4_lane0_dp_tx_preset);
int iSetGEN4_PHY_CAP_REG24_gen4_lane7_up_tx_preset(unsigned int ugen4_lane7_up_tx_preset);
int iSetGEN4_PHY_CAP_REG24_gen4_lane7_dp_tx_preset(unsigned int ugen4_lane7_dp_tx_preset);
int iSetGEN4_PHY_CAP_REG24_gen4_lane6_up_tx_preset(unsigned int ugen4_lane6_up_tx_preset);
int iSetGEN4_PHY_CAP_REG24_gen4_lane6_dp_tx_preset(unsigned int ugen4_lane6_dp_tx_preset);
int iSetGEN4_PHY_CAP_REG24_gen4_lane5_up_tx_preset(unsigned int ugen4_lane5_up_tx_preset);
int iSetGEN4_PHY_CAP_REG24_gen4_lane5_dp_tx_preset(unsigned int ugen4_lane5_dp_tx_preset);
int iSetGEN4_PHY_CAP_REG24_gen4_lane4_up_tx_preset(unsigned int ugen4_lane4_up_tx_preset);
int iSetGEN4_PHY_CAP_REG24_gen4_lane4_dp_tx_preset(unsigned int ugen4_lane4_dp_tx_preset);
int iSetGEN4_PHY_CAP_REG28_gen4_lane11_up_tx_preset(unsigned int ugen4_lane11_up_tx_preset);
int iSetGEN4_PHY_CAP_REG28_gen4_lane11_dp_tx_preset(unsigned int ugen4_lane11_dp_tx_preset);
int iSetGEN4_PHY_CAP_REG28_gen4_lane10_up_tx_preset(unsigned int ugen4_lane10_up_tx_preset);
int iSetGEN4_PHY_CAP_REG28_gen4_lane10_dp_tx_preset(unsigned int ugen4_lane10_dp_tx_preset);
int iSetGEN4_PHY_CAP_REG28_gen4_lane9_up_tx_preset(unsigned int ugen4_lane9_up_tx_preset);
int iSetGEN4_PHY_CAP_REG28_gen4_lane9_dp_tx_preset(unsigned int ugen4_lane9_dp_tx_preset);
int iSetGEN4_PHY_CAP_REG28_gen4_lane8_up_tx_preset(unsigned int ugen4_lane8_up_tx_preset);
int iSetGEN4_PHY_CAP_REG28_gen4_lane8_dp_tx_preset(unsigned int ugen4_lane8_dp_tx_preset);
int iSetGEN4_PHY_CAP_REG2C_gen4_lane15_up_tx_preset(unsigned int ugen4_lane15_up_tx_preset);
int iSetGEN4_PHY_CAP_REG2C_gen4_lane15_dp_tx_preset(unsigned int ugen4_lane15_dp_tx_preset);
int iSetGEN4_PHY_CAP_REG2C_gen4_lane14_up_tx_preset(unsigned int ugen4_lane14_up_tx_preset);
int iSetGEN4_PHY_CAP_REG2C_gen4_lane14_dp_tx_preset(unsigned int ugen4_lane14_dp_tx_preset);
int iSetGEN4_PHY_CAP_REG2C_gen4_lane13_up_tx_preset(unsigned int ugen4_lane13_up_tx_preset);
int iSetGEN4_PHY_CAP_REG2C_gen4_lane13_dp_tx_preset(unsigned int ugen4_lane13_dp_tx_preset);
int iSetGEN4_PHY_CAP_REG2C_gen4_lane12_up_tx_preset(unsigned int ugen4_lane12_up_tx_preset);
int iSetGEN4_PHY_CAP_REG2C_gen4_lane12_dp_tx_preset(unsigned int ugen4_lane12_dp_tx_preset);

#endif // __HIPCIEC_RP_CFGSPACE_2_C_UNION_DEFINE_H__
